IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 19

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

3.3
3.3.1
lowing technologies:
supported:
sources can be from T1, T2 or T3.
detect whether the signal is PECL or LVDS. The clock sources can be
from T1, T2 or T3.
Functional Description
IDT82V3285
Altogether 5 clocks and 1 frame sync signal are input to the device.
The device provides 5 input clock ports.
According to the input port technology, the input ports support the fol-
According to the input clock source, the following clock sources are
IN1, IN2 and IN5 support CMOS input signal only and the clock
IN3 and IN4 support PECL/LVDS input signal only and automatically
• PECL/LVDS
• CMOS
• T1: Recovered clock from STM-N or OC-n
• T2: PDH network synchronization timing
• T3: External synchronization reference timing
INPUT CLOCKS & FRAME SYNC SIGNAL
INPUT CLOCKS
19
Table 3: Related Bit / Register in Chapter 3.3
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
bit. During reset, the default value of the IN_SONET_SDH bit is deter-
mined by the SONET/SDH pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/SDH pin takes no effect.
3.3.2
pin. It is a CMOS input. The input frequency should match the setting in
the SYNC_FREQ[1:0] bits.
chronization. Refer to
details.
SYNC_FREQ[1:0]
IN_SONET_SDH
For SDH and SONET networks, the default frequency is different.
A 2 kHz, 4 kHz or 8 kHz frame sync signal is input on the EX_SYNC1
The frame sync input signal is used for frame sync output signal syn-
Bit
FRAME SYNC INPUT SIGNALS
Chapter 3.13.2 Frame SYNC Output Signals
INPUT_MODE_CNFG
Register
April 11, 2007
Address (Hex)
WAN PLL
09
for