IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 8

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

List of Figures
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 20
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 21
Figure 5. External Fast Selection ................................................................................................................................................................................ 23
Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 24
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 30
Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 31
Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 39
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 39
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 40
Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 40
Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 41
Figure 14. IDT82V3285 Power Decoupling Scheme ................................................................................................................................................... 43
Figure 15. Typical Application ...................................................................................................................................................................................... 44
Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 46
Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 47
Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 48
Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 49
Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 50
Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 51
Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 52
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 53
Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 53
Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 54
Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 55
Figure 27. Recommended PECL Input Port Line Termination .................................................................................................................................. 130
Figure 28. Recommended PECL Output Port Line Termination ................................................................................................................................ 130
Figure 29. Recommended LVDS Input Port Line Termination .................................................................................................................................. 132
Figure 30. Recommended LVDS Output Port Line Termination ................................................................................................................................ 132
Figure 31. Output Wander Generation ...................................................................................................................................................................... 136
Figure 32. Input / Output Clock Timing ...................................................................................................................................................................... 137
Figure 33. Output Clock Timing ................................................................................................................................................................................. 138
List of Figures
8
April 11, 2007