IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 60

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

Table 41: Register List and Map (Continued)
Programming Information
IDT82V3285
Address
(Hex)
5A
5B
5C
5D
5E
6A
6D
58
59
5F
60
61
62
63
64
65
66
67
68
69
T0_DPLL_LOCKED_BW_DAMPING_
CNFG - T0 DPLL Locked Bandwidth &
Damping Factor Configuration
T0_BW_OVERSHOOT_CNFG - T0
DPLL Bandwidth Overshoot Configu-
ration
PHASE_LOSS_COARSE_LIMIT_CNF
G - Phase Loss Coarse Detector Limit
Configuration *
PHASE_LOSS_FINE_LIMIT_CNFG -
Phase Loss Fine Detector Limit Con-
figuration *
T0_HOLDOVER_MODE_CNFG - T0
DPLL Holdover Mode Configuration
T0_HOLDOVER_FREQ[7:0]_CNFG -
T0 DPLL Holdover Frequency Config-
uration 1
T0_HOLDOVER_FREQ[15:8]_CNFG
- T0 DPLL Holdover Frequency Con-
figuration 2
T0_HOLDOVER_FREQ[23:16]_CNFG
- T0 DPLL Holdover Frequency Con-
figuration 3
T4_DPLL_APLL_PATH_CNFG - T4
DPLL & APLL Path Configuration
T4_DPLL_LOCKED_BW_DAMPING_
CNFG - T4 DPLL Locked Bandwidth &
Damping Factor Configuration
CURRENT_DPLL_FREQ[7:0]_STS -
DPLL Current Frequency Status 1 *
CURRENT_DPLL_FREQ[15:8]_STS -
DPLL Current Frequency Status 2 *
CURRENT_DPLL_FREQ[23:16]_STS
- DPLL Current Frequency Status 3 *
DPLL_FREQ_SOFT_LIMIT_CNFG
DPLL Soft Limit Configuration
DPLL_FREQ_HARD_LIMIT[7:0]_CNF
G - DPLL Hard Limit Configuration 1
DPLL_FREQ_HARD_LIMIT[15:8]_CN
FG - DPLL Hard Limit Configuration 2
CURRENT_DPLL_PHASE[7:0]_STS -
DPLL Current Phase Status 1 *
CURRENT_DPLL_PHASE[15:8]_STS
- DPLL Current Phase Status 2 *
T0_T4_APLL_BW_CNFG - T0 / T4
APLL Bandwidth Configuration
OUT1_FREQ_CNFG - Output Clock 1
Frequency Configuration
Register Name
-
PH_LOS_L
T_PH_LOS
AUTO_BW
FREQ_LIM
COARSE_
FINE_PH_
LOS_LIMT
MAN_HOL
T0_DPLL_LOCKED_DAMPING[2:0]
T4_DPLL_LOCKED_DAMPING[2:0]
IMT_EN
DOVER
_SEL
Bit 7
_EN
-
FAST_LOS
WIDE_EN
AUTO_AV
OUT1_PATH_SEL[3:0]
T4_APLL_PATH[3:0]
Output Configuration Registers
Bit 6
_SW
G
-
-
FAST_AVG
MULTI_PH
_APP
T0_APLL_BW[1:0]
Bit 5
60
-
-
DPLL_FREQ_HARD_LIMT[15:8]
CURRENT_DPLL_FREQ[23:16]
DPLL_FREQ_HARD_LIMT[7:0]
T0_HOLDOVER_FREQ[23:16]
CURRENT_DPLL_FREQ[15:8]
T0_HOLDOVER_FREQ[15:8]
CURRENT_DPLL_FREQ[7:0]
T0_HOLDOVER_FREQ[7:0]
CURRENT_PH_DATA[15:8]
CURRENT_PH_DATA[7:0]
MULTI_PH
_8K_4K_2
READ_AV
K_EN
DPLL_FREQ_SOFT_LIMT[6:0]
Bit 4
G
-
-
-
T4_GSM_GPS_16E1_1
TEMP_HOLDOVER_M
T0_LIMT
Bit 3
T0_DPLL_LOCKED_BW[4:0]
-
6T1_SEL[1:0]
-
-
ODE[1:0]
PH_LOS_COARSE_LIMT[3:0]
OUT1_DIVIDER[3:0]
Bit 2
-
-
-
PH_LOS_FINE_LIMT[2:0]
T4_12E1_24T1_E3_T3
T4_DPLL_LOCKED_B
T4_APLL_BW[1:0]
Bit 1
-
-
_SEL[1:0]
W[1:0]
Bit 0
-
-
April 11, 2007
WAN PLL
Reference
P 106
P 107
P 109
P 108
P 110
P 110
P 111
P 111
P 112
P 113
P 113
P 113
P 114
P 114
P 114
P 115
P 115
P 115
P 116
P 117
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