IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 59

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

Table 41: Register List and Map (Continued)
Programming Information
IDT82V3285
Address
(Hex)
4A
4B
4C
4D
4E
41
42
44
45
48
4F
50
51
52
53
54
55
56
57
IN_FREQ_READ_CH_CNFG - Input
Clock Frequency Read Channel
Selection
IN_FREQ_READ_STS - Input Clock
Frequency Read Value
IN1_IN2_STS - Input Clock 1 & 2 Sta-
tus
IN3_IN4_STS - Input Clock 3 & 4 Sta-
tus
IN5_STS - Input Clock 5 Status
INPUT_VALID1_STS - Input Clocks
Validity 1
INPUT_VALID2_STS - Input Clocks
Validity 2
REMOTE_INPUT_VALID1_CNFG
Input Clocks Validity Configuration 1
REMOTE_INPUT_VALID2_CNFG
Input Clocks Validity Configuration 2
PRIORITY_TABLE1_STS - Priority
Status 1 *
PRIORITY_TABLE2_STS - Priority
Status 2 *
T0_INPUT_SEL_CNFG - T0 Selected
Input Clock Configuration
T4_INPUT_SEL_CNFG - T4 Selected
Input Clock Configuration
OPERATING_STS - DPLL Operating
Status
T0_OPERATING_MODE_CNFG - T0
DPLL Operating Mode Configuration
T4_OPERATING_MODE_CNFG - T4
DPLL Operating Mode Configuration
T0_DPLL_APLL_PATH_CNFG - T0
DPLL & APLL Path Configuration
T0_DPLL_START_BW_DAMPING_C
NFG - T0 DPLL Start Bandwidth &
Damping Factor Configuration
T0_DPLL_ACQ_BW_DAMPING_CNF
G - T0 DPLL Acquisition Bandwidth &
Damping Factor Configuration
Register Name
-
-
EX_SYNC
_ALARM_
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
T0_DPLL_START_DAMPING[2:0]
T0_DPLL_ACQ_DAMPING[2:0]
MON
Bit 7
-D
HIGHEST_PRIORITY_VALIDATED[3:0]
-
-
-
-
-
-
-
-
-
-
-
T0 / T4 DPLL State Machine Control Registers
T0 / T4 DPLL & APLL Configuration Registers
T0 / T4 DPLL Input Clock Selection Registers
T4_LOCK_
IN2_FREQ
IN4_FREQ
T4_DPLL_
_HARD_A
_HARD_A
T0_APLL_PATH[3:0]
LARM
LARM
LOCK
Bit 6
T0
-
-
-
-
-
-
-
-
-
CTIVITY_A
CTIVITY_A
SOFT_FRE
IN4_VALID IN3_VALID IN2_VALID IN1_VALID
T0_FOR_T
IN2_NO_A
IN4_NO_A
T0_DPLL_
Q_ALARM
LARM
LARM
Bit 5
59
4
-
-
-
-
-
-
-
SOFT_FRE
T4_TEST_
T4_DPLL_
Q_ALRAM
IN2_PH_L
OCK_ALA
IN4_PH_L
OCK_ALA
IN_FREQ_VALUE[7:0]
T0_PH
Bit 4
RM
RM
-
-
-
-
-
-
-
IN[4:1]
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0
T0_DPLL_
T0_GSM_OBSAI_16E1
LOCK
Bit 3
_16T1_SEL[1:0]
T0_DPLL_START_BW[4:0]
-
-
-
-
-
-
-
CURRENTLY_SELECTED_INPUT[3:0]
T0_DPLL_ACQ_BW[4:0]
IN_FREQ_READ_CH[3:0]
IN1_FREQ
IN3_FREQ
IN5_FREQ
IN5_VALID
T0_DPLL_OPERATING_MODE[2:0]
_HARD_A
_HARD_A
_HARD_A
T0_INPUT_SEL[3:0]
T4_INPUT_SEL[3:0]
LARM
LARM
LARM
Bit 2
IN5
T0_OPERATING_MODE[2:0]
T4_OPERATING_MODE[2:0]
]
CTIVITY_A
CTIVITY_A
CTIVITY_A
IN1_NO_A
IN3_NO_A
IN5_NO_A
T0_12E1_24T1_E3_T3
LARM
LARM
LARM
Bit 1
-
-
-
-
_SEL[1:0]
IN1_PH_L
OCK_ALA
IN3_PH_L
OCK_ALA
IN5_PH_L
OCK_ALA
Bit 0
RM
RM
RM
-
-
-
-
April 11, 2007
WAN PLL
Reference
P 100
P 101
P 102
P 102
P 103
P 104
P 105
Page
P 91
P 92
P 93
P 94
P 95
P 96
P 96
P 96
P 97
P 97
P 98
P 99