IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 49

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

5.3
Microprocessor Interface
Table 34: Read Timing Characteristics in Intel Mode
IDT82V3285
Note:
* Timing with RDY. If RDY is not used, t
Symbol
t
t
t
t
t
pw1
pw2
su1
su2
t
t
t
t
t
t
t
t
t
t
out
T
d1
d2
d4
d5
d6
h1
h2
h3
TI
in
INTEL MODE
(RD rising edge to RD falling edge, or RD rising edge to WR falling edge)
AD[7:0]
Time between consecutive Read-Read or Read-Write accesses
A[6:0]
RDY
CS
WR
RD
RD rising edge to AD[7:0] high impedance delay time
pw1
Valid address after RD rising edge hold time
CS rising edge to RDY release delay time
Valid RD after RDY rising edge hold time
is 3.5T + 10.
Valid CS after RD rising edge hold time
RD rising edge to RDY low delay time
Valid address to valid CS setup time
One cycle time of the master clock
Valid RD to valid data delay time
Valid CS to valid RDY delay time
Valid CS to valid RD setup time
High-Z
Valid RDY pulse width low
High-Z
Valid RD pulse width low
Delay of output pad
Delay of input pad
t
su1
Parameter
Figure 19. Intel Read Timing Diagram
t
d2
t
su2
t
d1
address
t
49
pw2
t
pw1
data
t
h3
4.5T + 10 *
4.5T + 10
t
t
Min
d4
h1
>T
0
0
0
0
0
t
h2
t
d5
12.86
Typ
High-Z
t
13
10
13
13
d6
5
5
High-Z
3.5T + 10
Max
April 11, 2007
WAN PLL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns