IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 7

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

IDT82V3285
WAN PLL
Table 49: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 129
Table 50: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 131
Table 51: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 132
Table 52: Output Clock Jitter Generation .................................................................................................................................................................. 133
Table 53: Output Clock Phase Noise ......................................................................................................................................................................... 134
Table 54: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 134
Table 55: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 134
Table 56: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 134
Table 57: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 134
Table 58: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 135
Table 59: T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 135
Table 60: Input/Output Clock Timing 3 ...................................................................................................................................................................... 137
Table 61: Output Clock Timing .................................................................................................................................................................................. 138
List of Tables
7
April 11, 2007