IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 5

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

Table of Contents
9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 128
IDT82V3285
8.3 HEATSINK EVALUATION .......................................................................................................................................................................... 127
9.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 128
9.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 128
9.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 129
9.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 133
9.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 136
9.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 137
9.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 138
ORDERING INFORMATION .......................................................................................................................................... 143
9.3.1
9.3.2
CMOS Input / Output Port ............................................................................................................................................................ 129
PECL / LVDS Input / Output Port ................................................................................................................................................ 130
9.3.2.1
9.3.2.2
PECL Input / Output Port ................................................................................................................................................ 130
LVDS Input / Output Port ................................................................................................................................................ 132
5
April 11, 2007
WAN PLL