IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 57

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

Table 41: Register List and Map (Continued)
Programming Information
IDT82V3285
Address
(Hex)
0B
7E
0C
0D
0E
1A
13
7F
0F
10
12
16
17
18
19
1F
23
24
25
27
11
MON_SW_PBO_CNFG - Frequency
Monitor, Input Clock Selection & PBO
Control
MS_SL_CTRL_CNFG - Master Slave
Control
PROTECTION_CNFG - Register Pro-
tection Mode Configuration
MPU_SEL_CNFG - Microprocessor
Interface Mode Configuration
INTERRUPT_CNFG - Interrupt Config-
uration
INTERRUPTS1_STS - Interrupt Status
1
INTERRUPTS2_STS - Interrupt Status
2
INTERRUPTS3_STS - Interrupt Status
3
INTERRUPTS1_ENABLE_CNFG
Interrupt Control 1
INTERRUPTS2_ENABLE_CNFG
Interrupt Control 2
INTERRUPTS3_ENABLE_CNFG
Interrupt Control 3
IN1_CNFG - Input Clock 1 Configura-
tion
IN2_CNFG - Input Clock 2 Configura-
tion
IN3_IN4_HF_DIV_CNFG - Input Clock
3 & 4 High Frequency Divider Configu-
ration
IN3_CNFG - Input Clock 3 Configura-
tion
IN4_CNFG - Input Clock 4 Configura-
tion
IN5_CNFG - Input Clock 5 Configura-
tion
PRE_DIV_CH_CNFG - DivN Divider
Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider
Division Factor Configuration 1
PRE_DIVN[14:8]_CNFG
Divider Division Factor Configuration 2
IN1_IN2_SEL_PRIORITY_CNFG
Input Clock 1 & 2 Priority Configuration
*
Register Name
-
DivN
-
-
-
-
ATING_MO
ATING_MO
FREQ_MO
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
T0_OPER
EX_SYNC
T0_OPER
EX_SYNC
Input Clock Frequency & Priority Configuration Registers
_ALARM
_ALARM
N_CLK
Bit 7
DE
DE
IV
IV
IV
IV
IV
-
-
-
-
-
-
-
IN4_DIV[1:0]
IN2_SEL_PRIORITY[3:0]
T0_MAIN_
T0_MAIN_
G_TO_TD
REF_FAIL
REF_FAIL
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOS_FLA
T4_STS
T4_STS
Bit 6
ED
ED
O
-
-
-
-
-
-
Interrupt Registers
ULTR_FAS
T_SW
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
Bit 5
57
-
-
-
-
-
-
-
-
-
PROTECTION_DATA[7:0]
PRE_DIVN_VALUE[7:0]
INPUT_TO
INPUT_TO
EXT_SW
Bit 4
_T4
_T4
-
-
-
-
-
-
-
PRE_DIVN_VALUE[14:8]
IN[4:1]
IN[4:1]
PBO_FRE
Bit 3
Z
-
-
-
-
-
-
-
-
PRE_DIV_CH_VALUE[3:0]
IN1_SEL_PRIORITY[3:0]
PBO_EN
Bit 2
IN5
IN5
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
-
-
-
-
-
MPU_SEL_CNFG[2:0]
HZ_EN
Bit 1
-
-
-
-
-
-
-
-
IN3_DIV[1:0]
FREQ_MO
N_HARD_
MS_SL_C
INT_POL
Bit 0
TRL
EN
-
-
-
-
-
-
April 11, 2007
WAN PLL
Reference
Page
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P 68
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