IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 26

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

Table 12: Related Bit / Register in Chapter 3.7
3.7.3
not be locked in T0 DPLL within a certain period. This period can be cal-
culated as follows:
INn_PH_LOCK_ALARM bit (1 ≤ n ≤ 5).
selected by the PH_ALARM_TIMEOUT bit:
Functional Description
Note: * The setting in the 5A and 5B registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
IDT82V3285
A phase lock alarm will be raised when the selected input clock can
The phase lock alarm is indicated by the corresponding
The phase lock alarm can be cleared by the following two ways, as
Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]
PHASE LOCK ALARM (T0 ONLY)
INn_PH_LOCK_ALARM (
T0_DPLL_SOFT_FREQ_ALARM
T4_DPLL_SOFT_FREQ_ALARM
DPLL_FREQ_HARD_LIMT[15:0]
DPLL_FREQ_SOFT_LIMT[6:0]
PH_LOS_COARSE_LIMT[3:0]
COARSE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
PH_LOS_FINE_LIMT[2:0]
FINE_PH_LOS_LIMT_EN
TIME_OUT_VALUE[5:0]
PH_ALARM_TIMEOUT
FREQ_LIMT_PH_LOS
MULTI_FACTOR[1:0]
T0_DPLL_LOCK
T4_DPLL_LOCK
FAST_LOS_SW
T4_T0_SEL
WIDE_EN
T4_STS
T4_STS
Bit
1
2
1 ≤ n ≤ 5
)
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG,
PHASE_LOSS_COARSE_LIMIT_CNFG
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG
26
IN1_IN2_STS, IN3_IN4_STS, IN5_STS
PHASE_ALARM_TIME_OUT_CNFG
PHASE_LOSS_FINE_LIMIT_CNFG
DPLL_FREQ_SOFT_LIMIT_CNFG
INTERRUPTS3_ENABLE_CNFG
DPLL locking.
can not be locked.
T4_T0_REG_SEL_CNFG
The selected input clock with a phase lock alarm is disqualified for T0
Note that no phase lock alarm is raised if the T4 selected input clock
INPUT_MODE_CNFG
INTERRUPTS3_STS
• Be cleared when a ‘1’ is written to the corresponding
• Be cleared after the period (= TIME_OUT_VALUE[5:0] X
OPERATING_STS
INn_PH_LOCK_ALARM bit;
MULTI_FACTOR[1:0] in seconds) which starts from when the
alarm is raised.
Register
Address (Hex)
44 ~ 45, 48
67, 66
5B *
5A *
April 11, 2007
52
65
0F
12
08
09
07
WAN PLL