EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 273

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 8: External Memory Interfaces in Stratix III Devices
Stratix III External Memory Interface Features
© March 2010 Altera Corporation
Table 8–9. DLL Reference Clock Input for EP3SL200, EP3SE260 and EP3SL340 Devices
(2)
Figure 8–12
into the DLL to a chain of up to 16 delay elements. The phase comparator compares
the signal coming out of the end of the delay chain block to the input reference clock.
The phase comparator then issues the upndn signal to the Gray-code counter. This
signal increments or decrements a 6-bit delay setting (DQS delay settings) that
increases or decreases the delay through the delay element chain to bring the input
reference clock and the signals coming out of the delay element chain in phase.
DLL0
DLL1
DLL2
DLL3
Notes to
(1) PLLs L1, L3, L4, B2, R1, R3, R4, and T2 are not available for the EP3SL200 H780 package.
(2) PLLs L1, L4, R1 and R4 are not available for the EP3SL200 F1152 package.
DLL
Table
shows a simple block diagram of the DLL. The input reference clock goes
8–9:
(Top/Bottom)
CLK12P
CLK13P
CLK14P
CLK15P
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
CLKIN
(Left/Right)
CLK10P
CLK11P
CLK10P
CLK11P
CLK0P
CLK1P
CLK2P
CLK3P
CLK0P
CLK1P
CLK2P
CLK3P
CLK8P
CLK9P
CLK8P
CLK9P
CLKIN
(Top/Bottom)
PLL_T1
PLL_B1
PLL_B2
PLL_T2
PLL
Stratix III Device Handbook, Volume 1
(Left/Right)
PLL_R3
PLL_R4
PLL_R1
PLL_R2
PLL_L1
PLL_L2
PLL_L3
PLL_L4
PLL
(Note
8–25
1),