EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 375

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
Jam STAPL
Device Configuration Pins
Table 11–13. Stratix III Configuration Pin Summary
© March 2011 Altera Corporation
TDI
TMS
TCK
TRST
TDO
CRC_ERROR
DATA0
DATA[7..1]
INIT_DONE
CLKUSR
nSTATUS
nCE
CONF_DONE
nCONFIG
PORSEL
ASDO
nCSO
DCLK
—
nIO_PULLUP
nCEO
Description
f
Jam STAPL, JEDEC standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or configuration
of programmable devices and testing of electronic systems, using the IEEE 1149.1
JTAG interface. Jam STAPL is a freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP
state machine.
For more information about JTAG and Jam STAPL in embedded environments, refer
to
download the jam player, visit the Altera web site at www.altera.com.
The following tables describe the connections and functionality of all the
configuration-related pins on the Stratix III devices.
Stratix III configuration pins and their power supply.
AN 425: Using Command-Line Jam STAPL Solution for Device
Input/Output
bi-directional
bi-directional
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Dedicated
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
—
(Part 1 of 2)
V
V
V
Powered By
C CPGM
C CP GM
C CP GM
V
V
V
V
V
Pull-up
Pull-up
Pull-up
Pull-up
V
V
V
V
V
V
V
V
V
CC PD
CC PD
CC PD
CC PD
CC PD
Table 11–13
/V
/V
/V
C CP GM
C CP GM
C CP GM
C CP GM
C CP GM
C CP GM
C CP GM
C CP GM
C CP GM
CC IO
(2)
(2)
CC IO
CC IO
(2)
(2)
(2)
(3)
(3)
(3)
Stratix III Device Handbook, Volume 1
Programming. To
summarizes the
All modes except JTAG
Configuration Mode
Optional, all modes
Optional, all modes
All modes
All modes
All modes
All modes
All modes
All modes
All modes
Optional
PS, FPP
JTAG
JTAG
JTAG
JTAG
JTAG
FPP
AS
AS
AS
11–43