CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 23
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CY7C67300-100AXI
Manufacturer Part Number
CY7C67300-100AXI
Description
IC USB HOST/PERIPH CNTRL 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Type
Host Programmable Embedded USBr
Datasheet
1.CY7C67300-100AXI.pdf
(99 pages)
Specifications of CY7C67300-100AXI
Package / Case
100-LQFP
Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1865
CY7C67300-100AXI
CY7C67300-100AXI
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Memory Diagnostic Register [0xC03E] [W]
Table 33. Memory Diagnostic Register
Register Description
The Memory Diagnostic register provides control of diagnostic
modes.
Memory Arbitration Select (Bits[10:8])
The Memory Arbitration Select field is defined in
Table 34. Memory Arbitration Select
Monitor Enable (Bit 0)
The Monitor Enable bit enables or disables monitor mode. In
monitor mode the internal address bus is echoed to the external
address pins.
1: Enable monitor mode
0: Disable monitor mode
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Memory Arbitration
Select [3:0]
101
100
010
001
000
111
110
011
15
0
7
0
-
-
Memory Arbitration Timing
1/8, 7 of every 8 cycles dead
2/8, 6 of every 8 cycles dead
3/8, 5 of every 8 cycles dead
4/8, 4 of every 8 cycles dead
5/8, 3 of every 8 cycles dead
6/8, 2 of every 8 cycles dead
7/8, 1 of every 8 cycles dead
8/8, all cycles available
14
0
6
0
-
-
Reserved
13
Table
0
5
0
-
-
34.
Reserved
12
0
4
0
-
-
Reserved
Write all reserved bits with ’0’.
External Memory Registers
There are four registers dedicated to controlling the external
memory interface. Each of these registers are covered in this
section and are summarized in
Table 35. External Memory Control Registers
Extended Page 1 Map Register
Extended Page 2 Map Register
Upper Address Enable Register
External Memory Control Register
11
0
3
0
-
-
Register Name
10
W
0
2
0
-
Table
Arbitration
Memory
Select
W
9
0
1
0
-
35.
0xC018
0xC01A
0xC038
0xC03A
Address
CY7C67300
Monitor
Enable
Page 23 of 99
W
W
8
0
0
0
R/W
R/W
R/W
R/W
R/W
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