CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 45
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CY7C67300-100AXI
Manufacturer Part Number
CY7C67300-100AXI
Description
IC USB HOST/PERIPH CNTRL 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Type
Host Programmable Embedded USBr
Datasheet
1.CY7C67300-100AXI.pdf
(99 pages)
Specifications of CY7C67300-100AXI
Package / Case
100-LQFP
Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1865
CY7C67300-100AXI
CY7C67300-100AXI
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Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses trigger this interrupt.
1: Enable EP1 Transaction Done interrupt
0: Disable EP1 Transaction Done interrupt
EP0 Interrupt Enable (Bit 0)
The EP0 Interrupt Enable bit enables or disables endpoint zero
(EP0) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied Endpoint:
Device n Address Register [W]
■
■
Table 70. Device n Address Register
Register Description
The Device n Address register holds the device address
assigned by the host. This register initializes to the default
address 0 at reset but must be updated by firmware when the
host assigns a new address. Only USB data sent to the address
contained in this register gets a respond—all others are ignored.
Device n Status Register [R/W]
■
■
Table 71. Device n Status Register
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Device 1 Address Register 0xC08E
Device 2 Address Register 0xC0AE
Device 1 Status Register 0xC090
Device 2 Status Register 0xC0B0
EP7 Interrupt
VBUS Inter-
...Reserved
Flag
R/W
Flag
R/W
rupt
15
15
X
X
0
7
0
7
-
-
EP6 Interrupt
ID Interrupt
Flag
R/W
Flag
R/W
14
14
W
X
X
0
6
0
6
-
EP5 Interrupt
Flag
R/W
13
13
W
X
0
5
0
X
5
-
-
EP4 Interrupt
Flag
R/W
12
12
W
X
0
4
0
X
4
-
-
Reserved...
Reserved
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses trigger this interrupt.
1: Enable EP0 Transaction Done interrupt
0: Disable EP0 Transaction Done interrupt
Reserved
Write all reserved bits with ’0’.
Address (Bits [6:0])
The Address field contains the USB address of the device
assigned by the host.
Reserved
Write all reserved bits with ’0’.
EP3 Interrupt
Address
Flag
R/W
11
11
W
X
0
3
0
X
3
-
-
EP2 Interrupt
Flag
R/W
10
10
W
X
0
X
2
-
2
0
-
Interrupt Flag
EP1 Interrupt
SOF/EOP
Flag
R/W
R/W
W
X
9
0
X
1
-
1
0
9
CY7C67300
Reset Interrupt
EP0 Interrupt
Page 45 of 99
Flag
R/W
Flag
R/W
W
X
8
0
X
0
-
0
0
8
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