CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 72

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

SPI Transmit Count Register [0xC0DA] [R/W]
Table 116. SPI Transmit Count Register
Register Description
The SPI Transmit Count register designates the block byte
length for the SPI transmit DMA transfer.
Count (Bits [10:0])
The Count field sets the count for the SPI transmit DMA transfer.
SPI Receive Address Register [0xC0DC [R/W]
Table 117. SPI Receive Address Register
Register Description
The SPI Receive Address register is issued as the base address
for the SPI Receive DMA.
SPI Receive Count Register [0xC0DE] [R/W]
Table 118. SPI Receive Count Register
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
R/W
R/W
R/W
15
15
15
0
7
0
0
7
0
0
7
0
-
-
R/W
R/W
R/W
R/W
14
14
14
0
6
0
0
6
0
0
6
0
-
-
Reserved
Reserved
R/W
R/W
R/W
R/W
13
13
13
0
5
0
0
5
0
0
5
0
-
-
R/W
R/W
R/W
R/W
12
12
12
0
4
0
0
4
0
0
4
0
-
-
Address...
...Address
...Count
...Count
Reserved
Write all reserved bits with ’0’.
Address (Bits [15:0])
The Address field sets the base address for the SPI receive
DMA.
R/W
R/W
R/W
R/W
11
11
11
0
0
3
0
3
0
0
3
0
-
-
R/W
R/W
R/W
R/W
R/W
R/W
10
10
10
0
0
2
0
0
2
0
2
0
Count...
Count...
R/W
R/W
R/W
R/W
R/W
R/W
9
0
9
0
1
0
9
0
1
0
1
0
CY7C67300
Page 72 of 99
R/W
R/W
R/W
R/W
R/W
R/W
8
0
8
0
0
0
8
0
0
0
0
0
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