CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 46
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CY7C67300-100AXI
Manufacturer Part Number
CY7C67300-100AXI
Description
IC USB HOST/PERIPH CNTRL 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Type
Host Programmable Embedded USBr
Datasheet
1.CY7C67300-100AXI.pdf
(99 pages)
Specifications of CY7C67300-100AXI
Package / Case
100-LQFP
Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1865
CY7C67300-100AXI
CY7C67300-100AXI
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Register Description
The Device n Status register provides status information for
device operation. Pending interrupts can be cleared by writing a
‘1’ to the corresponding bit. This register can be accessed by the
HPI interface.
VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG
VBUS interrupt (only for Port 1A). When enabled this interrupt
triggers on both the rising and falling edge of VBUS at 4.4V. This
bit is only available for Device 1 and is a reserved bit in Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
ID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID
interrupt (only for Port 1A). When enabled this interrupt triggers
on both the rising and falling edge of the OTG ID pin. This bit is
only available for Device 1 and is a reserved bit in Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP
received interrupt triggered.
1: Interrupt triggered
0: Interrupt did not trigger
Reset Interrupt Flag (Bit 8)
The Reset Interrupt Flag bit indicates if the USB Reset Detected
interrupt triggered.
1: Interrupt triggered
0: Interrupt did not trigger
EP7 Interrupt Flag (Bit 7)
The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7)
Transaction Done interrupt triggered. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied EP: send/receive
ACK, send STALL, Timeout occurs, IN Exception Error, or OUT
Exception Error. In addition, if the NAK Interrupt Enable bit in the
Device n Endpoint Control register is set, this interrupt also
triggers when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
Document #: 38-08015 Rev. *J
EP6 Interrupt Flag (Bit 6)
The EP6 Interrupt Flag bit indicates if the endpoint six (EP6)
Transaction Done interrupt triggered. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied EP: send/receive
ACK, send STALL, Timeout occurs, IN Exception Error, or OUT
Exception Error. In addition, if the NAK Interrupt Enable bit in the
Device n Endpoint Control register is set, this interrupt also
triggers when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP5 Interrupt Flag (Bit 5)
The EP5 Interrupt Flag bit indicates if the endpoint five (EP5)
Transaction Done interrupt triggered. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied EP: send/receive
ACK, send STALL, Timeout occurs, IN Exception Error, or OUT
Exception Error. In addition, if the NAK Interrupt Enable bit in the
Device n Endpoint Control register is set, this interrupt also
triggers when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP4 Interrupt Flag (Bit 4)
The EP4 Interrupt Flag bit indicates if the endpoint four (EP4)
Transaction Done interrupt triggered. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied EP: send/receive
ACK, send STALL, Timeout occurs, IN Exception Error, or OUT
Exception Error. In addition, if the NAK Interrupt Enable bit in the
Device n Endpoint Control register is set, this interrupt also
triggers when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP3 Interrupt Flag (Bit 3)
The EP3 Interrupt Flag bit indicates if the endpoint three (EP3)
Transaction Done interrupt triggered. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied EP: send/receive
ACK, send STALL, Timeout occurs, IN Exception Error, or OUT
Exception Error. In addition, if the NAK Interrupt Enable bit in the
Device n Endpoint Control register is set, this interrupt also
triggers when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
CY7C67300
Page 46 of 99
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