CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 74
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CY7C67300-100AXI
Manufacturer Part Number
CY7C67300-100AXI
Description
IC USB HOST/PERIPH CNTRL 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Type
Host Programmable Embedded USBr
Datasheet
1.CY7C67300-100AXI.pdf
(99 pages)
Specifications of CY7C67300-100AXI
Package / Case
100-LQFP
Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1865
CY7C67300-100AXI
CY7C67300-100AXI
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UART Status Register [0xC0E2] [R]
Table 122. UART Status Register
Register Description
The UART Status register is a read only register that indicates
the status of the UART buffer.
Receive Full (Bit 1)
The Receive Full bit indicates whether the receive buffer is full.
It can be programmed to interrupt the CPU as interrupt #5 when
the buffer is full. This can be done though the UART bit of the
Interrupt Enable register (0xC00E). This bit is automatically
cleared when data is read from the UART Data register.
1: Receive buffer full
0: Receive buffer empty
UART Data Register [0xC0E4] [R/W]
Table 123. UART Data Register
Register Description
The UART Data register contains data to be transmitted or
received from the UART port. Data written to this register starts
a data transmission and also causes the UART Transmit Full
Flag of the UART Status register to set. When data received on
the UART port is read from this register, the UART Receive Full
Flag of the UART Status register is cleared.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
15
15
0
0
7
0
-
7
0
-
-
R/W
14
14
6
0
-
0
0
6
0
-
-
R/W
5
0
-
13
13
0
0
5
0
-
-
...Reserved
4
0
-
R/W
12
12
0
0
4
0
-
-
Reserved...
Reserved
Transmit Full (Bit 0)
The Transmit Full bit indicates whether the transmit buffer is full.
It can be programmed to interrupt the CPU as interrupt #4 when
the buffer is empty. This can be done though the UART bit of the
Interrupt Enable register (0xC00E). This bit is automatically set
to ‘1’ after data is written by EZ-Host to the UART Data register
(to be transmitted). This bit is automatically cleared to ‘0’ after
the data is transmitted.
1: Transmit buffer full (transmit busy)
0: Transmit buffer is empty and ready for a new byte of data
Data (Bits [7:0])
The Data field is where the UART data to be transmitted or
received is located.
Reserved
Write all reserved bits with ’0’.
Data
3
0
-
R/W
11
11
0
3
0
0
-
-
2
0
-
R/W
10
10
0
2
0
0
-
-
Receive Full
R
1
0
R/W
9
0
1
0
9
0
-
-
CY7C67300
Transmit Full
Page 74 of 99
R
R/W
0
0
8
0
0
0
-
8
0
-
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