CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 92
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CY7C67300-100AXI
Manufacturer Part Number
CY7C67300-100AXI
Description
IC USB HOST/PERIPH CNTRL 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Type
Host Programmable Embedded USBr
Datasheet
1.CY7C67300-100AXI.pdf
(99 pages)
Specifications of CY7C67300-100AXI
Package / Case
100-LQFP
Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1865
CY7C67300-100AXI
CY7C67300-100AXI
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Price
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Company:
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Quantity:
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Part Number:
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Manufacturer:
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Company:
Part Number:
CY7C67300-100AXIT
Manufacturer:
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Hardware CTS/RTS Handshake
t
t
T = 1/48 MHz.
When RTS/CTS hardware handshake is enabled, transmission can be help off by deasserting HSS_CTS at least 1.5T before
HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit.
HSS_RTS is deasserted in the third data bit time.
An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.
Register Summary
Table 142. Register Summary
Document #: 38-08015 Rev. *J
R/W
R
R
W
R/W
R/W
R.W
R/W
R/W
R
R/W
R
R/W
R/W
R/W
CTSsetup
CTShold
Address Register
0x0140
0x0142
1: 0x0144
2: 0x0148
0x02n0
0x02n2
0x02n4
0x02n6
0xC000
0xC002
0xC004
0xC008
0xC00A
0x02n8
0xC006
: HSS_CTS hold time after START bit = 0 ns min.
HSS_CTS
HSS_TxD
HSS_RTS
: HSS_CTS setup time before HSS_RTS = 1.5T min.
HPI Breakpoint
Interrupt Routing
SIEXmsg
Device n Endpoint n Control
Device n Endpoint n Address
Device n Endpoint n Count
Device n Endpoint n Status
Device n Endpoint n Count Result Result...
CPU Flags
Bank
Hardware Revision
GPIO Control
CPU Speed
Power Control
Start of transmission delayed until HSS_CTS goes high
tCTSsetup
Bit 15
Bit 7
Address...
...Address
VBUS to HPI
Enable
Resume2 to
HPI Enable
Data...
...Data
Reserved
IN/OUT
Ignore Enable
Address...
...Address
Reserved
...Count
Reserved
Stall
Flag
...Result
Reserved...
...Reserved
Address...
...Address
Revision...
...Revision
Enable
HSS
Enable
Reserved...
.Reserved
Host/Device
2B Wake
Enable
HPI
Wake Enable
Write Protect
tCTShold
Bit 14
Bit 6
ID to HPI
Enable
Resume1 to
HPI Enable
Sequence
Select
NAK
Flag
UD
HSS XD
Enable
Host/Device
2A Wake
Enable
Reserved
Bit 13
Bit 5
SOF/EOP2 to
HPI Enable
Reserved
Stall
Enable
Length
Exception Flag
Reserved
SPI
Enable
Host/Device
1B Wake
Enable
Bit 12
Bit 4
SOF/EOP2 to
CPU Enable
ISO
Enable
Setup
Flag
Global Inter-
rupt Enable
SPI XD
Enable
Host/Device
1A Wake
Enable
GPI
Wake Enable
Bit 11
Bit 3
SOF/EOP1 to
HPI Enable
Done2 to HPI
Enable
NAK Interrupt
Enable
Overflow
Flag
Sequence
Status
Negative
Flag
Reserved
SAS
Enable
Interrupt 1
Polarity
Select
CPU Speed
OTG
Wake
Enable
Reserved
Start of transmission not delayed by HSS_CTS
tCTSsetup
Bit 10
Bit 2
SOF/EOP1 to
CPU Enable
Done1 to HPI
Enable
Direction
Select
Underflow
Flag
Timeout
Flag
Overflow
Flag
Mode
Select
Interrupt 1
Enable
Reserved
Boost 3V
OK
Bit 9
Bit 1
Reset2 to HPI
Enable
Reset1 to HPI
Enable
Enable
Count...
OUT
Exception Flag
Error
Flag
Carry
Flag
Interrupt 0
Polarity
Select
HSS
Wake
Enable
Sleep
Enable
tCTShold
Bit 8
Bit 0
HPI Swap 1
Enable
HPI Swap 0
Enable
ARM
Enable
IN
Exception Flag
ACK
Flag
Zero
Flag
Interrupt 0
Enable
SPI
Wake
Enable
Halt
Enable
CY7C67300
Page 92 of 99
xxxx xxxx
Default High
Default Low
0000 0000
0000 0000
0001 0100
0000 0000
xxxx xxxx
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xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
000x xxxx
0000 0001
000x xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 1111
0000 0000
0000 0000
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