CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 40
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CY7C67300-100AXI
Manufacturer Part Number
CY7C67300-100AXI
Description
IC USB HOST/PERIPH CNTRL 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Type
Host Programmable Embedded USBr
Datasheet
1.CY7C67300-100AXI.pdf
(99 pages)
Specifications of CY7C67300-100AXI
Package / Case
100-LQFP
Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1865
CY7C67300-100AXI
CY7C67300-100AXI
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Register Description
The Device n Endpoint n Address register is used as the base
pointer into memory space for the current Endpoint transaction.
There are a total of eight endpoints for each of the two ports. All
endpoints have the same definition for their Device n Endpoint n
Address register.
Device n Endpoint n Count Register [R/W]
■
■
■
■
■
■
■
■
Table 65. Device n Endpoint n Count Register
Register Description
The Device n Endpoint n Count register designates the
maximum packet size that can be received from the host for OUT
transfers for a single endpoint. This register also designates the
packet size to be sent to the host in response to the next IN token
for a single endpoint. The maximum packet length is 1023 bytes
in ISO mode. There are a total of eight endpoints for each of the
two ports. All endpoints have the same definition for their Device
n Endpoint n Count register.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284]
Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294]
Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4]
Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4]
Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4]
Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4]
Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4]
Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4]
R/W
15
X
X
7
-
R/W
14
X
X
6
-
R/W
13
X
X
5
-
Reserved
R/W
12
X
X
4
-
...Count
Address (Bits [15:0])
The Address field sets the base address for the current trans-
action on a signal endpoint.
Count (Bits [9:0])
The Count field sets the current transaction packet length for a
single endpoint.
Reserved
Write all reserved bits with ’0’.
R/W
11
X
3
X
-
R/W
10
X
2
X
-
R/W
R/W
X
X
1
9
Count...
CY7C67300
Page 40 of 99
R/W
R/W
X
X
0
8
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