CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 64
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CY7C67300-100AXI
Manufacturer Part Number
CY7C67300-100AXI
Description
IC USB HOST/PERIPH CNTRL 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Type
Host Programmable Embedded USBr
Datasheet
1.CY7C67300-100AXI.pdf
(99 pages)
Specifications of CY7C67300-100AXI
Package / Case
100-LQFP
Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1865
CY7C67300-100AXI
CY7C67300-100AXI
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HPI Status Port [] [HPI: R]
Table 103. HPI Status Port
Register Description
The HPI Status Port provides the external host processor with
the MailBox status bits plus several SIE status bits. This register
is not accessible from the on-chip CPU. The additional SIE status
bits are provided to aid external device driver firmware devel-
opment, and are not recommended for applications that do not
have an intimate relationship with the on-chip BIOS.
Reading from the HPI Status Port does not result in a CPU HPI
interface memory access cycle. The external host may continu-
ously poll this register without degrading the CPU or DMA perfor-
mance.
VBUS Flag (Bit 15)
The VBUS Flag bit is a read only bit that indicates whether OTG
VBus is greater than 4.4V. After turning on VBUS, firmware must
wait at least 10 µs before this reading this bit.
1: OTG VBus is greater than 4.4V
0: OTG VBus is less than 4.4V
ID Flag (Bit 14)
The ID Flag bit is a read only bit that indicates the state of the
OTG ID pin.
SOF/EOP2 Flag (Bit 12)
The SOF/EOP2 Flag bit is a read only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP1 Flag (Bit 10)
The SOF/EOP1 Flag bit is a read only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Reset2 Flag (Bit 9)
The Reset2 Flag bit is a read only bit that indicates if a USB
Reset interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Resume2
VBUS
Flag
Flag
15
R
X
R
X
7
Resume1
Flag
Flag
14
ID
R
X
R
X
6
Reserved
SIE2msg
13
X
R
X
5
-
SOF/EOP2
SIE1msg
Flag
12
R
X
R
X
4
Mailbox In Flag (Bit 8)
The Mailbox In Flag bit is a read only bit that indicates if a
message is ready in the incoming mailbox. This interrupt clears
when the on-chip CPU reads from the HPI Mailbox register.
1: Interrupt triggered
0: Interrupt did not trigger
Resume2 Flag (Bit 7)
The Resume2 Flag bit is a read only bit that indicates if a USB
resume interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Resume1 Flag (Bit 6)
The Resume1 Flag bit is a read only bit that indicates if a USB
resume interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
SIE2msg (Bit 5)
The SIE2msg Flag bit is a read only bit that indicates if the
CY7C67300 CPU wrote to the SIE2msg register. This bit is
cleared on an HPI read.
1: The SIE2msg register was written by the CY7C67300 CPU
0: The SIE2msg register was not written by the CY7C67300 CPU
SIE1msg (Bit 4)
The SIE1msg Flag bit is a read only bit that indicates if the
CY7C67300 CPU wrote to the SIE1msg register. This bit is
cleared on an HPI read.
1: The SIE1msg register was written by the CY7C67300 CPU
0: The SIE1msg register was not written by the CY7C67300 CPU
Done2 Flag (Bit 3)
In host mode the Done2 Flag bit is a read only bit that indicates
if a host packet done interrupt occurs on Host 2. In device mode
this read only bit indicates if an any of the endpoint interrupts
occur on Device 2. Firmware needs to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Reserved
Done2
Flag
11
X
R
X
3
-
SOF/EOP1
Done1
Flag
Flag
10
R
X
R
X
2
Reset2
Reset1
Flag
Flag
R
X
R
X
9
1
CY7C67300
Mailbox Out
Mailbox In
Page 64 of 99
Flag
Flag
R
X
R
X
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