CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 76

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Mode Select (Bit 8)
The Mode Select bit selects between continuous PWM cycling
and one shot mode. The default is continuous repeat.
1: Enable One Shot mode. The mode runs the number of counter
cycles set in the PWM Cycle Count register and then stops.
0: Enable Continuous mode. Runs in continuous mode and
starts over after the PWM cycle count is reached.
PWM 3 Polarity Select (Bit 7)
The PWM 3 Polarity Select bit selects the polarity for PWM 3.
1: Sets the polarity to active HIGH or rising edge pulse
0: Sets the polarity to active LOW
PWM 2 Polarity Select (Bit 6)
The PWM 2 Polarity Select bit selects the polarity for PWM 2.
1: Sets the polarity to active HIGH or rising edge pulse
0: Sets the polarity to active LOW
PWM 1 Polarity Select (Bit 5)
The PWM 1 Polarity Select bit selects the polarity for PWM 1.
1: Sets the polarity to active HIGH or rising edge pulse
0: Sets the polarity to active LOW
PWM Maximum Count Register [0xC0E8] [R/W]
Table 127. PWM Maximum Count Register
Register Description
The PWM Maximum Count register designates the maximum
window for each pulse cycle. Each count tick is based on the
clock frequency set in the PWM Control register.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
15
0
7
0
-
R/W
14
0
6
0
-
R/W
13
0
5
0
-
Reserved
R/W
12
0
4
0
-
...Count
PWM 0 Polarity Select (Bit 4)
The PWM 0 Polarity Select bit selects the polarity for PWM 0.
1: Sets the polarity to active HIGH or rising edge pulse
0: Sets the polarity to active LOW
PWM 3 Enable (Bit 3)
The PWM 3 Enable bit enables or disables PWM 3.
1: Enable PWM 3
0: Disable PWM 3
PWM 2 Enable (Bit 2)
The PWM 2 Enable bit enables or disables PWM 2.
1: Enable PWM 2
0: Disable PWM 2
PWM 1 Enable (Bit 1)
The PWM 1 Enable bit enables or disables PWM 1.
1: Enable PWM 1
0: Disable PWM 1
PWM 0 Enable (Bit 0)
The PWM 0 Enable bit enables or disables PWM 0.
1: Enable PWM 0
0: Disable PWM 0
Count (Bits [9:0])
The Count field sets the maximum cycle time.
Reserved
Write all reserved bits with ’0’.
R/W
11
0
3
0
-
R/W
10
0
2
0
-
R/W
R/W
9
0
1
0
Count...
CY7C67300
Page 76 of 99
R/W
R/W
8
0
0
0
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