CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 32
![IC USB HOST/PERIPH CNTRL 100LQFP](/photos/6/70/67051/428-100-tqfp_14x14x1_4_sml.jpg)
CY7C67300-100AXI
Manufacturer Part Number
CY7C67300-100AXI
Description
IC USB HOST/PERIPH CNTRL 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Type
Host Programmable Embedded USBr
Datasheet
1.CY7C67300-100AXI.pdf
(99 pages)
Specifications of CY7C67300-100AXI
Package / Case
100-LQFP
Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1865
CY7C67300-100AXI
CY7C67300-100AXI
Available stocks
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Manufacturer
Quantity
Price
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Company:
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Quantity:
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Part Number:
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Company:
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CY7C67300-100AXIT
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Quantity:
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Sequence Status (Bit 3)
The Sequence Status bit indicates the state of the last received
data toggle from the device. Firmware is responsible for
monitoring and handling the sequence status. The Sequence bit
is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to
‘0’ when an error is detected in the transaction and the Error bit
is set.
1: DATA1
0: DATA0
Timeout Flag (Bit 2)
The Timeout Flag bit indicates if a timeout condition occurred for
the last transaction. A timeout condition can occur when a device
either takes too long to respond to a USB host request or takes
too long to respond with a handshake.
1: Timeout occurred
0: Timeout did not occur
Error Flag (Bit 1)
The Error Flag bit indicates a transaction failed for any reason
other than the following: timeout, receiving a NAK, or receiving
Host n PID Register [W]
■
■
Table 53. Host n PID Register
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Host 1 PID Register 0xC086
Host 2 PID Register 0xC0A6
15
W
0
7
0
-
14
W
0
6
0
-
PID Select
13
W
0
5
0
-
12
W
0
4
0
-
Reserved
a STALL. Overflow and Underflow are not considered errors and
do not affect this bit. CRC5 and CRC16 errors result in an Error
flag along with receiving incorrect packet types.
1: Error detected
0: No error detected
ACK Flag (Bit 0)
The ACK Flag bit indicates two different conditions depending on
the transfer type. For non-isochronous transfers, this bit repre-
sents a transaction ending by receiving or sending an ACK
packet. For isochronous transfers, this bit represents a
successful transaction that is not represented by an ACK packet.
1: For non-isochronous transfers, the transaction was ACKed.
For isochronous transfers, the transaction was completed
successfully
0: For non-isochronous transfers, the transaction was not
ACKed. For isochronous transfers, the transaction did not
complete successfully
11
W
0
3
0
-
10
W
0
-
2
0
Endpoint Select
W
9
0
-
1
0
CY7C67300
Page 32 of 99
W
8
0
-
0
0
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