CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 62
![IC USB HOST/PERIPH CNTRL 100LQFP](/photos/6/70/67051/428-100-tqfp_14x14x1_4_sml.jpg)
CY7C67300-100AXI
Manufacturer Part Number
CY7C67300-100AXI
Description
IC USB HOST/PERIPH CNTRL 100LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Type
Host Programmable Embedded USBr
Datasheet
1.CY7C67300-100AXI.pdf
(99 pages)
Specifications of CY7C67300-100AXI
Package / Case
100-LQFP
Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current
80 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1865
CY7C67300-100AXI
CY7C67300-100AXI
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ID to HPI Enable (Bit 14)
The ID to HPI Enable bit routes the OTG ID interrupt to the HPI
port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to HPI Enable (Bit 13)
The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt
to the HPI port.
1: Route signal to HPI port
0 : Do not route signal to HPI port
SOF/EOP2 to CPU Enable (Bit 12)
The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2
interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can
be routed to both the on-chip CPU and the HPI port, the firmware
must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU
0: Do not route signal to CPU
SOF/EOP1 to HPI Enable (Bit 11)
The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt
to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP1 to CPU Enable (Bit 10)
The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1
interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can
be routed to both the on-chip CPU and the HPI port, the firmware
must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU
0: Do not route signal to CPU
Reset2 to HPI Enable (Bit 9)
The Reset2 to HPI Enable bit routes the USB Reset interrupt that
occurs on Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
HPI Swap 1 Enable (Bit 8)
Both HPI Swap bits (bits 8 and 0) must be set to identical values.
When set to ‘00’, the most significant data byte goes to
HPI_D[15:8] and the least significant byte goes to HPI_D[7:0].
This is the default setting. By setting to ‘11’, the most significant
data byte goes to HPI_D[7:0] and the least significant byte goes
to HPI_D[15:8].
Document #: 38-08015 Rev. *J
Resume2 to HPI Enable (Bit 7)
The Resume2 to HPI Enable bit routes the USB Resume
interrupt that occurs on Host 2 to the HPI port instead of the
on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Resume1 to HPI Enable (Bit 6)
The Resume1 to HPI Enable bit routes the USB Resume
interrupt that occurs on Host 1 to the HPI port instead of the
on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Done2 to HPI Enable (Bit 3)
The Done2 to HPI Enable bit routes the Done interrupt for
Host/Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Done1 to HPI Enable (Bit 2)
The Done1 to HPI Enable bit routes the Done interrupt for
Host/Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Reset1 to HPI Enable (Bit 1)
The Reset1 to HPI Enable bit routes the USB Reset interrupt that
occurs on Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
HPI Swap 0 Enable (Bit 0)
Both HPI Swap bits (bits 8 and 0) must be set to identical values.
When set to ‘00’, the most significant data byte goes to
HPI_D[15:8] and the least significant byte goes to HPI_D[7:0].
This is the default setting. By setting to ‘11’, the most significant
data byte goes to HPI_D[7:0] and the least significant byte goes
to HPI_D[15:8].
CY7C67300
Page 62 of 99
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