MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 104
MC68030FE25C
Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Specifications of MC68030FE25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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MOTOROLA
<operand>sign-extended--The operand is sign extended; all bits of the upper
Notations for operations that have two operands, written <0Perand> <op>
<operand>, where <op> is one of the following:
Notation for single-operand operations:
Notation for other operations:
shifted by, rotated by--The source operand is shifted or rotated by the
If <condition> then--The condition is tested. If true, the operations
<operations> else
<operand>tested--The operand is compared to zero, and the con-
<operations>
-<operand>--The operand is logically complemented
STOP--Enter the stopped state, waiting for interrupts
TRAP--Equivalent to Format/Offset Word J (SSP); SSP-2
MC68030 USER'S MANUAL
el--The two operands are exchanged
Q--Logical exclusive OR
+--The operands are added
- - - T h e destination operand is subtracted from the
x--The operands are multiplied
<--Relational test, true if source operand is less than
>--Relational test, true if source operand is greater
A--Logical AND
-
V--Logical OR
0--The source operand is moved to the destination
The source operand is divided by the destination
than destination operand
the lower portion
false and the optional "else" clause is present,
the operations after "else" are performed. If the
tion performs no operation. Refer to the Bcc in-
operand
source operand
operand
destination operand
operand
dition codes are set appropriately
J SSP; PC i (SSP); S S P - 4 0 SSP; SR t (SSP);
SSP-2 I) SSP; (vector) 0 PC
after "then" are performed. If the condition is
condition is false and else is omitted, the instruc-
struction description as an example.
number of positions specified by the second
portion are made equal to the high-order bit of
3-19
3
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