MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 212

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.3.5 Synchronous Write Cycle
MOTOROLA
State 3
A synchronous write cycle is terminated differently from an asynchronous
write cycle and the data strobe may not be useful. Otherwise, the cycles
clock (CLK) may be used as the timing signal for latching the data. In addition,
there is.no time from the latest assertion of AS and the required assertion
State 2
assert and respond to the same signal, in the same sequence. STERM is
asserted by the external device to terminate a synchronous write cycle. The
discussion of STERM in the preceding section applies to write cycles as well
as to read cYCles.
DS is not asserted for two-clock synchronous write cycles; therefore, the
The selected device uses R/W, SIZ0-SIZ1, A0-A1, and CLOUT to place its
A0-A1. During S2, the processor drives DBEN active to enable external
timing of DBEN may prevent its use. At the beginning of S2, the processor
the incoming data at the end of S2. If the selected data is not to be cached
for the current cycle or if the device cannot supply 32 bits, CIIN must be
the synchronous input setup and hold times for all rising edges of the clock
while AS is asserted. If STERM is negated at the beginning of S2, wait
thereafter until it is recognized. Once STERM is recognized, data is latched
The processor negates AS, DS, and DBEN during $3. It holds the address
valid during $3 to simplify memory interfaces. R/W, SIZ0-SIZ1, and FC0-FC2
The external device must keep its data asserted throughout the synchron-
two clocks after asserting STERM; otherwise, the processor may inad-
vertently use STERM for the next bus cycle.
(D24-D31, D16-D23, D8-D15, and D0-D7) are selected by SlZ0-SlZl and
data buffers. In systems that use two-clock synchronous bus cycles, the
samples the level of STERM. If STERM is recognized, the processor latches
asserted at the same time as STERM. In addition, the state of CBACK is
latched when STERM is recognized.
Since ClIN, CBACK, and STERM are synchronous signals, they must meet
states are inserted after S2, and STERM is sampled on every rising edge
on the next falling edge of the clock (corresponding to the beginning of
S3).
also remain valid throughout $3.
ous hold time for data from the beginning of $3. The device must remove
its data within one clock after asserting STERM and negate STERM within
information on the data bus. Any or all of the byte sections of the data bus
MC68030 USER'S MANUAL
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