MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 98

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

3.2.10 M e m o r y M a n a g e m e n t Unit Instructions
3.2.11 Multiprocessor Instructions
MOTOROLA
The TAS, CAS, and CAS2 instructions coordinate the operations of processors
The PFLUSH instructions flush the address translation caches (ATCs) and
can optionally select only nonglobal entries for flushing. PTEST performs a
search of the address translation tables, storing results in the MMU status
in multiprocessing systems. These instructions use read-modify-write bus
cycles to ensure uninterrupted updating of memory. Coprocessor instructions
control the coprocessor operations. Table 3-11 lists these instructions.
I
register and loading the entry into the ATC. Table 3-10 summarizes these
instructions.
TAS
cpBcc
cpGEN
cp RESTORE
cpScc
cpTRAPcc
PFLUSHA
PFLUSHA.N
PFLUSH
PFLUSH.N
PTEST
CAS
CAS2
cpDBcc
cpSAVE
Instruction
Instruction ] Operand Syntax ] Operand Size I
Table 3-11. Multiprocessor Operations (Read-Modify-Write)
Dcl:Dc2,(Rn}:(Rn)OUl:Du2, 8,16,32
Operand Syntax
User Defined
Dc,Du,<ea>
(label),Dn
#(data)
(label)
<ea>
none
none
none
{An)
(An)
(An)
(ea)
(ea)
(ea)
Table 3-10. MMU Instructions
MC68030 USER'S M A N U A L
Operand Size
User Defined
8,16,32
16, 32
16, 32
none
none
none
none
none
none
none
none
16
8
8
Read-Modify-Write
Coprocessor
~
I
I destination - - Dc $ CC; if Z then Du 0 destination
I destination - - 0;
Invalidate all ATC
Invalidate all nonglobal ATC
Invalidate ATC entries at effective address
Invalidate nonglobal ATC entries at effective address
Information about
dual operand CAS
if cpcc true then pc - d i PC
restore coprocessor state from
save
if cpcc true then TRAPcc exception
if cpcc false then Dn - 1 I) Dn
ifDn ¢ - 1, then PC - d l P C
if cpcc true, then l's j destination; else O's I) destination
operand i
coprocessor state
coprocessor
set condition
entries
logical address I MMU
D
c
Operation
Operation
at (ea)
.
2
.
entries
~
codes; 1 I) destination [7]
(ea)
.
.
.
status register
.
3-13
3