MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 498

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
11.6.4
11.6.5 Jump Effective Address
The jump effective address table indicates the number of clock periods needed
for the processor to calculate the specified effective address for the JMP or
JSR instructions. Fetch time is only included for the first level of indirection
All timing data assumes two-clock reads and writes.
I
on memory indirect addressing modes. The effective addresses are divided
is outside the parentheses. The number of read, prefetch, and write cycles
is given inside the parentheses as (r/p/w). The read, prefetch, and write cycles
are included in the total clock cycle number.
I
I% (d8,An,Xn) or (d8,PC,Xn)
by their formats (refer to 2.5 Effective Address Encoding Summary). For
instruction-cache case and for no-cache case, the total number of clock cycles
;% (xxx).W
SINGLE EFFECTIVE ADDRESS INSTRUCTION FORMAT
% (An)
% (d16,An)
BRIEF FORMAT EXTENSION WORD
FULL FORMAT EXTENSION WORD(S) (CONTINUED)
'/o (xxx).L
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.
% = Total head for address timing includes the head time for the operation.
Calculate Immediate Effective Address (ciea) (Continued)
B -
#(data).W,([d32,B],d32)
#(data).L,([d32,B],d32)
#(data).W,([d32,B],l,d32)
#(data}.L,([d32,B],l,d32)
I -
Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing.
Index; 0, Xn
Address Mode
Address Mode
MC68030 USER'S MANUAL
I
I
I'÷°pheadl
2 + o p head
4 + o p head
2 + o p head
2 + o p head
Head I
Head
6
8
6
8
I
Tail
Tail
0
0
0
0
0
0
0
0
0
I I-Cache Case I No-Cache Casel
I
I-Cache Case I No-Cache Casel
I
20(1/0/0)
22(1/0/0)
20(1/0/0)
22(1/0/0)
2(0/0/0)
4(0/0/0)
2(0/0/0)
2(0/0/0)
,<0/0/01
2(0/0~0)
I ,(0,00
22(1/3/0)
24(1/4/0)
22(1/3/0)
24(1/4/0)
2(0/0,0)
4(0/0/0)
2(0/0,0)
11-35
I
11