MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 316

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9.2.2 Effect of RESET on M M U
9.2.3 Effect of M M U D I S on Address Translation
MOTOROLA
write access, when the modified bit of the ATC entry is not set, the memory
that neither TTx register matches and the access is not to CPU space, the
ATC provides the address translation to the bus controller under two con-
tions that cause the memory cycle to be aborted. In these cases, the bus
An MMU instruction (such as PMOVE) that flushes the ATC must be executed
to flush all existing valid entries from the ATC after a reset operation and
translation disabled, logical addresses are used as physical addresses. When
created the ATC entry, the memory access is aborted, and a bus error ex-
ception is taken.
also aborted, and a bus error exception is taken. For a write or read-modify-
cycle is aborted, a table search proceeds to set the modified bit in both the
ditions: 1) if a read access does not hit in either on-chip cache and 2) if a
write or read-modify-write access is not write protected.
The preceding description of the general flowchart specifies several condi-
cycle is aborted before the assertion of AS.
When the MC68030 is reset by the assertion of the RESET signal, the E bits
of the TC and TTx registers are cleared, disabling address translation. This
causes logical addresses to be passed through as physical addresses to the
and registers, the E bit of the TC register can be set, enabling address trans-
The assertion of MMUDIS prevents the MMU from performing searches of
the ATC and the execution unit from performing table searches. With address
an initial access to a long-word-aligned data operand that is larger than the
were used for the initial bus cycle (changing A0 and A1 appropriately). Thus,
hits in the ATC but a bus error was detected during the table search that
If an access results in an ATC hit but the access is either a write or read-
modify-write access and the page is write protected, the memory cycle is
page descriptor in memory and in the ATC, and the access is retried. If the
modified bit of the ATC entry is set and the bus error bit is not, assuming
bus controller, allowing an operating system to set up the translation tables
and MMU registers, as required. After it has initialized the translation tables
lation. A reset of the processor does not invalidate any entries in the ATC.
before translation is enabled.
addressed port size is performed, the successive bus cycles for additional
portions of the operand always use the same higher order address bits that
MC68030 USER'S MANUAL
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