MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 534

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MC68030FE25C

Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68030FE25C

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
12.3 BYTE SELECT LOGIC FOR THE MC68030
MOTOROLA
The architecture of the MC68030 allows it to support byte, word, and long-
word operand transfers to any 8-, 16-, or 32-bit data port regardless of align-
the data transfer accordingly, using multiple bus cycles when necessary.
The following signals control the MC68030 operand transfer mechanism'
ment. This feature allows the programmer to write code that is not bus-width
specific. When accessed, the peripheral or memory subsystem reports its
actual port size to the processor, and the MC68030 then dynamically sizes
dependent of software prejudices. The following paragraphs describe the
generation of byte select control signals that enable the dynamic bus sizing
Hardware designers also have the flexibility to choose implementations in-
mechanism, the transfer of differently sized operands, and the transfer of
misaligned operands to operate correctly.
DSACKO/DSACK]
• A1, A0 = Address lines. The most significant byte of the operand to be
• S!Z1, SIZ0 = Transfer size. Output of the MC68030. These indicate the
• R/W = Read/Write. Output of the MC68030. For byte select generation
START
AS
data from the device is cachable.
in MC68030 systems, R/W must be included in the logic if the
transferred is addressed directly.
Figure 12-5. Bus Cycle Timing Diagram
number of bytes of an operand remaining to be transferred
during a given bus cycle.
MC68030 USER'S MANUAL
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S
FPCP SPECIFICATION
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MPU SPECIFICATION
12-9
12

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