MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 277

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8
8-10
treated as unimplemented instructions with F-line opcodes when execution
tion vector number for an unimplemented instruction with an F-line opcode
with an F-line exception handler. Refer to SECTION 10 COPROCESSOR
equal to $0, and defined word patterns for subsequent words are legal MMU
attempted in user mode, a privilege violation exception is taken. The excep-
The word patterns with bits [15:12] equal to $F and bits [11:9] not equal to
zero are used for coprocessor instructions. When the processor identifies a
coprocessor instruction, it runs a bus cycle referencing CPU space type $2
cessors (1-7, according to bits [11:9]). If the addressed coprocessor is not
error signal, the instruction takes an unimplemented instruction (F-line op-
code) exception. The system can emulate the functions of the coprocessor
INTERFACE DESCRIPTION for more details.
An illegal instruction exception is also taken if a breakpoint acknowledge bus
cycle (see 7.4.2 Breakpoint Acknowledge Cycle) is terminated with the as-
sertion of the bus error signal. This implies that the external circuitry did not
supply an instruction word to replace the BKPT instruction word in the in-
struction pipe.
Instructions that have word patterns with bits [15:12] equal to $F, bits [11:9]
instructions. Instructions that have bits [15:12] of the first words equal to $F,
bits [11:9] equal to $0, and undefined patterns in subsequent words are
is attempted in supervisor mode. When execution of the same instruction is
is number 11.
(refer to 4.2 ADDRESS SPACE TYPES) and addressing one of seven copro-
included in the system and the cycle terminates with the assertion of the bus
tempts to execute an unimplemented instruction with an A-line opcode, an
Instruction word patterns with bits [15:12] equal to $A are referred to as
unimplemented instructions with A-line opcodes. When the processor at-
exception is generated with vector number 10, permitting efficient emulation
of unimplemented instructions.
MC68030 USER'S MANUAL
MOTOROLA