MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 471
MC68030FE25C
Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Specifications of MC68030FE25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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11-8
11.3.3 Average No-Cache Case
The nature of the instruction overlap and the fact that the heads of some
The average no-cache-case (NCC) time for an instruction takes into account
the time required for the microcode to execute plus the time required for all
external bus activity. This time is calculated assuming both caches miss and
the associated instruction prefetches require one external bus cycle per two
case time also assumes no overlap..All bus cycles are assumed to take two
clock periods. Average no-cache-case times for instructions and effective
address calculations are listed in 11.6 INSTRUCTION TIMING TABLES. Be-
cause the no-cache-case times assume no overlap, the head and tail values
listed in these tables do not apply to the no-cache-case values.
the value shown in the table is the average of the odd-word-aligned case
instructions equal the total instruction-cache-case time for those instructions
makes a zero net execution time possible. The execution time of an instruction
is completely absorbed by overlap with the previous instruction.
instruction prefetches. Refer to 11.2.2 Instruction Pipe. The average no-cache-
Since the actual no-cache-case time depends on the alignment of prefetches
associated with an instruction, both alignment cases were considered, and
and the even-word-aligned case (rounded up to an integral number of clocks).
Similarly, the number of prefetch bus cycles is the average of these two cases
rounded up to an integral number of bus cycles.
i
i
HEAD
Figure 11-3. Derivation of Instruction Overlap Time
I
I
t
MC68030 USER'S MANUAL
READ/WRITE BUS
TIME OR SYNC
/zC0DE TIME
CACHE CASE
I
BEST CASE
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WRITE BUS TIME
TAIL
MOTOROLA
t
I
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