MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 24
MC68030FE25C
Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Specifications of MC68030FE25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Number
MOTOROLA
Figure
10-41
10-42
10-43
10-44
10-45
11-1
11-2
11-3
11-5
11-4
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
i2-15
12-16
12-17
12-18
12-19
12-20
12-21
Take Mid-Instruction Exception Primitive Format ..................... 10-58
Take Post-Instruction Exception Primitive Format
MC68030 Pre-lnstruction Stack Frame .................................... 10-57
MC68030 Mid-Instruction Stack Frame .............. . ............. :. ..... 10-59
MC68030 Post-Instruction Stack Frame ................................... 10-60
32-Bit Data Bus Coprocessor Connection
Access Time Computation Diagram ....................................... 12-15
Additional Memory Enable Circuits ........................................ 12-21
Block Diagram - - Eight Independent Resources ...................... 11-3
Simultaneous Instruction Execution ....................................... 11-7
Derivation of Instruction Overlap Time ................................... 11-8
Processor Activity - - Even Alignment .................................... 11-9
Processor Activity - - Odd Alignment ..................................... 11-10
Signal Routing for Adapting the MC68030 to MC68020
Chip-Select Generation PAL .................................................. 12-8
PAL Equations ..................................................................... 12-8
Example MC68030 Byte Select PAL System Configuration ....... 12-12
Example Two-Clock Read, Three-Clock Write Memory Bank ..... 12-19
Example PAL Equation for Two-Clock Read and Write Memory
Additional Memory Enable Circuit ......................................... 12-29
Trace or Interrupt Exception .................................................. 12-38
Bus Cycle Timing Diagram .................................................... 12-9
MC68030 Byte Select PAL Equations ........ i ............................. 12-13
Example PAL Equations for Two-Clock Memory Bank .............. 12-20
Example Two-Clock Read and Write Memory Bank ................. 12-22
Example 2-1-1-1 Burst Mode Memory Bank at 20 MHz, 256K
Example 3-1-1-1 Pipelined Burst Mode Memory Bank at 20 MHz,
Example MC68030 Hardware Configuration with External
Example Early Termination Control Circuit ............................. 12-34
Other Exceptions ................................................................. 12-38
Normal Instruction Boundaries .............................................. 12-37
LIST OF ILLUSTRATIONS (Continued)
Designs ........................................................................... 12-2
256K Bytes ....................................................................... 12-28
Bank ................................................................................ 12-23
Bytes ............................................................................... 12-25
Physical Cache ................................................................. 12-33
MC68030 USER'S MANUAL
Title
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Number
Page
10-60
12-6
xxiii
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