MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 160

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

6.3.1.10 FREEZE INSTRUCTION CACHE.
6.3.1.11 ENABLE INSTRUCTION CACHE.
6.3.2 Cache Address Register
MOTOROLA
struction cache. When the FI bit is set and a miss occurs in the instruction
cache, the entry (or line) is not replaced. When the FI bit is cleared to zero,
a miss in the instruction cache causes the entry (or line) to be filled. A reset
operation clears the El bit. The supervisor normally enables the instruction
The CAAR is a 32-bit register shown in Figure 6-15. The index field (bits 7-2)
contains the address for the "clear cache entry" operations. The bits of this
field correspond to bits 7-2 of addresses; they specify the index and a long
word of a cache line. Although only the index field is used currently, all 32
operation clears the FI bit.
struction cache. When it is cleared, the instruction cache is disabled. A reset
cache, but it can clear El for system debugging or emulation, as required.
Disabling the instruction cache does not flush the entries. If it is enabled
again, the previously valid entries remain valid and may be used.
bits of the register are implemented and are reserved for use by Motorola.
l
31
CACHE FUNCTION ADDRESS
Figure 6-15. Cache Address Register
MC68030 USER'S MANUAL
Bit 1, the FI bit, is set to freeze the in-
Bit 0, the El bit, is set to enable the in-
8 7
[
INDEX
2 1
6-23
0