AD9957BSVZ Analog Devices Inc, AD9957BSVZ Datasheet - Page 16

• Manufacturer Part Number: AD9957BSVZ
• Description: IC DDS 1GSPS 14BIT IQ 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9957BSVZ

• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Frequency Range: 60MHz To 1GHz
• Rf Type: Quadrature
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465
• Rf Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 100
• Mounting: Surface Mount
• Case Height: 1mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9957/PCBZ - BOARD EVAL AD9957 QUADRATURE MOD
• Lead Free Status / Rohs Status: Compliant

AD9957
MODES OF OPERATION
OVERVIEW
The AD9957 has three basic operating modes.
•
•
•
The active mode is selected via the operating mode bits in
Control Function Register 1 (CFR1). Single tone mode allows
the device to operate as a sinusoidal generator with the DDS
driving the DAC directly.
Interpolating DAC mode bypasses the DDS, allowing the user
to deliver baseband data to the device at a sample rate lower
Quadrature modulation (QDUC) mode (default)
Interpolating DAC mode
Single tone mode
TxENABLE
PDCLK
I/Q IN
FTW
18
PW
TIMING AND CONTROL
PROGRAMMING
PARALLEL DATA
REGISTERS
3
18
16
16
18
QS
Q
IS
I
SERIAL I/O
PORT
INTERNAL CLOCK TIMING AND CONTROL
Figure 25. Detailed Block Diagram
I Q
RAM
Rev. B | Page 16 of 64
IS QS
OSK
AD9957
cos (ωt+θ)
θ
ω
sin (ωt+θ)
CLOCK
CONTROL
DDS
POWER
DOWN
than that of the DAC. An internal chain of rate interpolation
filters the user data and upsamples to the DAC sample rate.
Combined, the filters provide for programmable rate interpola-
tion while suppressing spectral images and retaining the original
baseband spectrum.
QDUC mode employs both the DDS and the rate interpolation
filters. In this case, two parallel banks of rate interpolation
filters allow baseband processing of in-phase and quadrature
(I/Q) signals with the DDS providing the carrier signal to be
modulated by the baseband signals. A detailed block diagram of
the AD9957 is shown in Figure 25.
The inverse sinc filter is available in all three modes.
2
2
SYSCLK
DAC GAIN
PLL
÷2
8
FACTOR
OUTPUT
SCALE
8-BIT
AUX
DAC
14-BIT
DAC
DAC_RSET
IOUT
IOUT
REFCLK_OUT
REF_CLK
REF_CLK
XTAL_SEL