AD9957BSVZ Analog Devices Inc, AD9957BSVZ Datasheet - Page 50

• Manufacturer Part Number: AD9957BSVZ
• Description: IC DDS 1GSPS 14BIT IQ 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9957BSVZ

• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Frequency Range: 60MHz To 1GHz
• Rf Type: Quadrature
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465
• Rf Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 100
• Mounting: Surface Mount
• Case Height: 1mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9957/PCBZ - BOARD EVAL AD9957 QUADRATURE MOD
• Lead Free Status / Rohs Status: Compliant

AD9957
REGISTER MAP AND BIT DESCRIPTIONS
REGISTER MAP
Note that the highest number found in the Bit Range column for each register in the following tables is the MSB and the lowest number is
the LSB for that register.
Table 13. Control Registers
Register
Name
(Serial
Address)
Control
Function
Register 1
CFR1
(0x00)
Control
Function
Register 2
CFR2
(0x01)
Control
Function
Register 3
CFR3
(0x02)
Auxiliary
DAC
Control
Register
(0x03)
I/O Update
Rate
Register
(0x04)
Bit
Range
(Internal
Address)
<31:24>
<23:16>
<15:8>
<7:0>
<31:24>
<23:16>
<15:8>
<7:0>
<31:24>
<23:16>
<15:8>
<7:0>
<31:24>
<23:16>
<15:8>
<7:0>
<31:24>
<23:16>
<15:8>
<7:0>
Bit 7
(MSB)
RAM
Enable
Manual
OSK
External
Control
Digital
Power-
Down
Blackfin
Interface
Mode
Active
Internal
I/O
Update
Active
Matched
Latency
Enable
REFCLK
Input
Divider
Bypass
I/O Update Rate Control
Open
Open
Open
Bit 6
Inverse
Sinc Filter
Enable
DAC Power-
Down
Blackfin Bit
Order
SYNC_CLK
Enable
Data
Assembler
Hold Last
Value
REFCLK
Input
Divider
ResetB
Open
Bit 5
Clear CCI
Autoclear
Phase
Accumulator
REFCLK Input
Power-Down
Blackfin
Early Frame
Sync Enable
PDCLK Rate
Control
Sync Timing
Validation
Disable
DRV0<1:0>
Rev. B | Page 50 of 64
Bit 4
RAM
Playback
Destination
Open
Aux DAC
Power-Down
Data Format
I/O Update Rate<31:24>
I/O Update Rate<23:16>
I/O Update Rate<15:8>
I/O Update Rate<7:0>
I
CP
N<6:0>
<2:0>
FSC<7:0>
Open
Open
Open
Bit 3
Clear Phase
Accumulator
External
Power-Down
Control
PDCLK
Enable
Open
Open
Open
Open
Open
Open
Open
Bit 2
Load ARR @
I/O Update
Auto
Power-Down
Enable
PDCLK
Invert
VCO SEL<2:0>
Bit 1
OSK
Enable
SDIO
Input
Only
TxEnable
Invert
Open
Operating Mode
Bit 0
(LSB)
Select
DDS
Sine
Output
Select
Auto-
OSK
LSB First
Registers
Read
Effective
FTW
Q-First
Data
Pairing
PLL
Enable
Open
Source
Enable
Profile
as ASF
Default
Value
0x00
0x00
0x00
0x00
0x00
0x40
0x08
0x20
0x1F
0x3F
0x40
0x00
0x00
0x00
0x7F
0x7F
0xFF
0xFF
0xFF
0xFF