AD9957BSVZ Analog Devices Inc, AD9957BSVZ Datasheet - Page 58

• Manufacturer Part Number: AD9957BSVZ
• Description: IC DDS 1GSPS 14BIT IQ 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9957BSVZ

• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Frequency Range: 60MHz To 1GHz
• Rf Type: Quadrature
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465
• Rf Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 100
• Mounting: Surface Mount
• Case Height: 1mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9957/PCBZ - BOARD EVAL AD9957 QUADRATURE MOD
• Lead Free Status / Rohs Status: Compliant

AD9957
Control Function Register 3 (CFR3)
Address 0x02, four bytes are assigned to this register.
Table 20. Bit Descriptions for CFR3 Register
Bit (s)
31:30
29:28
27
26:24
23:22
21:19
18:16
15
14
13:9
8
7:1
0
Auxiliary DAC Control Register
Address 0x03, four bytes are assigned to this register.
Table 21. Bit Descriptions for Auxiliary DAC Control Register
Bit(s)
31:8
7:0
I/O Update Rate Register
Address 0x04, four bytes are assigned to this register. This register is effective without the need for an I/O update.
Table 22. Bit Descriptions for I/O Update Rate Register5
Bit(s)
31:0
RAM Segment Register 0
Address 0x05, six bytes are assigned to this register. This register is effective without the need for an I/O update. This register is only
active if CFR1<31> = 1 and there is a Logic 0-to-Logic 1 transition on the RT pin.
Table 23. Bit Descriptions for RAM Segment Register 0
Bit(s)
47:32
31:22
21:16
15:6
5:3
2:0
Mnemonic
I/O Update Rate
Mnemonic
Open
FSC
Mnemonic
RAM Address Step
Rate 0
RAM End Address 0
Open
RAM Start Address 0
Open
RAM Playback Mode 0
Mnemonic
Open
DRV0
Open
VCO SEL
Open
I
Open
REFCLK Input Divider
Bypass
REFCLK Input Divider
ResetB
Open
PLL Enable
N
Open
CP
Description
Controls REFCLK_OUT pin (see Table 6 for details); default is 01b.
Selects frequency band of the VCO in the REFCLK PLL (see Table 7 for details); default is 111b.
Selects the charge pump current in the REFCLK PLL (see Table 8 for details); default is 111b.
0: input divider is selected (default).
1: input divider is bypassed.
0: input divider is reset.
1: input divider operates normally (default).
0: REFCLK PLL bypassed (default).
1: REFCLK PLL enabled.
This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is 0000000b.
Description
This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary DAC section);
default is 0xFF.
Description
This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM
address range.
This 10-bit number identifies the ending address for the RAM state machine.
This 10-bit number identifies the starting address for the RAM state machine.
This 3-bit number identifies the playback mode for the RAM state machine (see Table 5).
Description
Ineffective unless CFR2<23> = 1. This 32-bit number controls the automatic I/O update rate (see the
Automatic I/O Update section); default is 0xFFFFFFFF.
Rev. B | Page 58 of 64