AD9957BSVZ Analog Devices Inc, AD9957BSVZ Datasheet - Page 44

• Manufacturer Part Number: AD9957BSVZ
• Description: IC DDS 1GSPS 14BIT IQ 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9957BSVZ

• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Frequency Range: 60MHz To 1GHz
• Rf Type: Quadrature
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465
• Rf Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 100
• Mounting: Surface Mount
• Case Height: 1mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9957/PCBZ - BOARD EVAL AD9957 QUADRATURE MOD
• Lead Free Status / Rohs Status: Compliant

AD9957
SYNCHRONIZATION EXAMPLE
To accomplish the synchronization of multiple devices provide
each AD9957 with a SYNC_IN signal that is edge aligned across
all the devices. If the SYNC_IN signal is edge aligned at all devices,
and all devices have the same sync receiver delay and sync state
preset value, then they all have matching clock states (that is,
they are synchronized). Figure 59 shows this concept with three
AD9957s in synchronization. One device operates as a master
timing unit with the others synchronized to the master.
The master device must have its SYNC_IN pins included as part
of the synchronization distribution and delay equalization mecha-
nism. This ensures that the master maintains synchronous timing
with the other units.
The synchronization mechanism begins with the clock distribu-
tion and delay equalization block, which ensures that all devices
receive an edge-aligned REFCLK signal. However, even though
the REFCLK signal is edge aligned among all devices, this alone
does not guarantee that the clock state of each internal clock
AT REF_CLK
ALIGNED
INPUTS
EDGE
FPGA
FPGA
FPGA
DELAY EQUALIZATION
CLOCK DISTRIBUTION
(FOR EXAMPLE, AD951x)
Figure 59. Multichip Synchronization Example
AND
DATA
DATA
DATA
Rev. B | Page 44 of 64
SYNC
SYNC
SYNC
NUMBER 1
NUMBER 2
NUMBER 3
AD9957
AD9957
AD9957
IN
IN
IN
SOURCE
REF_CLK
REF_CLK
REF_CLK
CLOCK
SYNC
SYNC
SYNC
OUT
OUT
OUT
generator is coordinated with the others. This is the role of the
synchronization and delay equalization block. This block accepts
the SYNC_OUT signal generated by the master device and
redistributes it to the SYNC_IN input of the slave units (as well
as feeding it back to the master). The goal of the redistributed
SYNC_OUT signal from the master device is to deliver an edge-
aligned SYNC_IN signal to all of the sync receivers.
Assuming that all devices share the same REFCLK edge timing
(due to the clock distribution and delay equalization block) and
that all devices share the same SYNC_IN edge timing (due to
the synchronization and delay equalization block), then all
devices should be generating an internal sync pulse in unison
(assuming all have the same value for the sync receiver delay).
With the further stipulation that all devices have the same sync
state preset value, then the synchronized sync pulses cause all of
the devices to assume the same predefined clock state simultane-
ously. That is, all devices have their internal clocks fully
synchronized.
MASTER DEVICE
AT SYNC_IN
ALIGNED
INPUTS.
EDGE
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
SYNCHRONIZATION
DISTRIBUTION AND