AD9957BSVZ Analog Devices Inc, AD9957BSVZ Datasheet - Page 49

• Manufacturer Part Number: AD9957BSVZ
• Description: IC DDS 1GSPS 14BIT IQ 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9957BSVZ

• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Frequency Range: 60MHz To 1GHz
• Rf Type: Quadrature
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465
• Rf Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 100
• Mounting: Surface Mount
• Case Height: 1mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9957/PCBZ - BOARD EVAL AD9957 QUADRATURE MOD
• Lead Free Status / Rohs Status: Compliant

I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK
RELATIONSHIPS
The I/O_UPDATE pin is used to transfer data from the serial
I/O buffer to the active registers in the device. Data in the buffer
is inactive.
SYNC_CLK is a rising edge active signal. It is derived from the
system clock and a divide-by-4 frequency divider. SYNC_CLK,
which is externally provided, can be used to synchronize
external hardware to the AD9957 internal clocks.
I/O_UPDATE initiates the start of a buffer transfer. It can
be sent synchronously or asynchronously relative to the
SYNC_CLK. If the setup time between these signals is met,
then constant latency (pipeline) to the DAC output exists.
I/O BUFFERS
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
I/O_UPDATE
REGISTERS
SYNC_CLK
DATA IN
SYSCLK
DATA IN
N
N – 1
Figure 64. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers
A
B
N + 1
Rev. B | Page 49 of 64
For example, if repetitive changes to phase offset via the SPI
port is desired, the latency of those changes to the DAC output
is constant; otherwise, a time uncertainty of one SYNC_CLK
period is present.
By default, the I/O_UPDATE pin is an input that serves as a
strobe signal to allow synchronous update of the device oper-
ating parameters. A rising edge on I/O_UPDATE initiates
transfer of the register contents to the internal workings of
the device. Alternatively, the transfer of programmed data from
the programming registers to the internal hardware can be
accomplished by changing the state of the PROFILE[2:0] pins.
The timing diagram shown in Figure 64 depicts when the data
in the buffer is transferred to the active registers.
N
N + 2
N + 1
AD9957