AD9957BSVZ Analog Devices Inc, AD9957BSVZ Datasheet - Page 41

• Manufacturer Part Number: AD9957BSVZ
• Description: IC DDS 1GSPS 14BIT IQ 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9957BSVZ

• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Frequency Range: 60MHz To 1GHz
• Rf Type: Quadrature
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465
• Rf Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 100
• Mounting: Surface Mount
• Case Height: 1mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9957/PCBZ - BOARD EVAL AD9957 QUADRATURE MOD
• Lead Free Status / Rohs Status: Compliant

SYSCLK
The sync generator produces an LVDS-compatible clock signal
with a 50% duty cycle that appears at the SYNC_OUT pins. The
frequency of the SYNC_OUT signal can be one of two possible
rates. With the AD9957 programmed for any of the following
modes:
•
•
•
The frequency of SYNC_OUT is given by:
With the AD9957 programmed for the QDUC or interpolating
DAC mode and with the CCI filter not bypassed (that is, R>1)
the frequency of SYNC_OUT is given by
where R is the programmed interpolation factor of the CCI filter.
The signal at the SYNC_OUT pins is edge aligned with either
the rising or falling edge of the internal SYSCLK signal as deter-
mined by the Sync Polarity bit. Because the SYNC_OUT signal is
synchronized with the internal SYSCLK of the master device, the
master device SYSCLK serves as the reference timing source for
all slave devices.
The user can adjust the output delay of the SYNC_OUT signal
in steps of ~150 ps by programming the 5-bit sync generator
delay word via the serial I/O port. The programmable output
delay facilitates added edge timing flexibility to the overall
synchronization mechanism.
Single tone mode
Quadrature modulation mode with the CCI filter bypassed
(that is, interpolation factor is 1)
Interpolating DAC mode with the CCI filter bypassed (that
is, interpolation factor is 1)
f
f
SYNC
SYNC
POLARITY
÷16
SYNC
_
_
OUT
OUT
=
=
÷2R
0
1
f
f
SYSCLK
SYSCLK
32
16
Figure 56. Sync Generator
R
GENERATOR
ENABLE
D Q
SYNC
R
PROGAMMABLE
GENERATOR
DELAY
SYNC
DELAY
5
DRIVER
LVDS
10
9
SYNC_OUT
Rev. B | Page 41 of 64
SYNC RECEIVER
The sync receiver block (shown in Figure 57) is activated via the
Sync Receiver Enable bit. The sync receiver consists of three
subsections: the input delay and edge detection block, the
internal clock generator block, and the setup-and-hold valida-
tion block.
The clock generator block remains operational even when the
sync receiver is not enabled.
The sync receiver accepts an LVDS-compatible signal at the
SYNC_IN pins. Typically, the signal applied to the SYNC_IN
pins originates from the SYNC_OUT of another AD9957
functioning as a master timing unit. The sync receiver expects a
periodic synchronization pulse that meets certain frequency
requirements based on the operating mode of the AD9957.
When programmed for single tone mode, the frequency of
SYNC_IN must satisfy
where M is any integer greater than zero. When programmed
for quadrature modulation mode (using the parallel data port)
or interpolating DAC mode, the frequency of SYNC_IN must
satisfy
where R is the programmed CCI interpolation factor and M is
any integer greater than or equal to zero. When programmed
for quadrature modulation mode using the BlackFin interface,
the frequency of SYNC_IN must satisfy
where R is the programmed CCI interpolation factor and M is
any integer greater than or equal to zero.
f
f
f
SYNC
SYNC
SYNC
_
_
_
IN
IN
IN
=
=
=
16
32
f
SYSCLK
4
f
f
(
(
SYSCLK
SYSCLK
R
M
R
+
+
M
M
)
)
AD9957