AD9957BSVZ Analog Devices Inc, AD9957BSVZ Datasheet - Page 6

• Manufacturer Part Number: AD9957BSVZ
• Description: IC DDS 1GSPS 14BIT IQ 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9957BSVZ

• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Frequency Range: 60MHz To 1GHz
• Rf Type: Quadrature
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465
• Rf Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 100
• Mounting: Surface Mount
• Case Height: 1mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9957/PCBZ - BOARD EVAL AD9957 QUADRATURE MOD
• Lead Free Status / Rohs Status: Compliant

AD9957
Parameter
NOISE SPECTRAL DENSITY (NSD)
TWO-TONE INTERMODULATION DISTORTION (IMD)
MODULATOR CHARACTERISTICS
SERIAL PORT TIMING CHARACTERISTICS
I/O_UPDATE/PROFILE<2:0>/RT TIMING CHARACTERISTICS
I/Q INPUT TIMING CHARACTERISTICS
MISCELLANEOUS TIMING CHARACTERISTICS
DATA LATENCY (PIPELINE DELAY)
Single Tone
Input Data
Maximum SCLK Frequency
Minimum SCLK Pulse Width
Maximum SCLK Rise/Fall Time
Minimum Data Setup Time to SCLK
Minimum Data Hold Time to SCLK
Maximum Data Valid Time in Read Mode
Minimum Pulse Width
Minimum Setup Time to SYNC_CLK
Minimum Hold Time to SYNC_CLK
Maximum PDCLK Frequency
Minimum I/Q Data Setup Time to PDCLK
Minimum I/Q Data Hold Time to PDCLK
Minimum TxEnable Setup Time to PDCLK
Minimum TxEnable Hold Time to PDCLK
Wake-Up Time
Minimum Reset Pulse Width High
Data Latency Single Tone Mode
f
f
f
WCDMA—FDD (TM1), 3.84 MHz Bandwidth,
Carrier Feedthrough
OUT
OUT
OUT
f
f
f
f
Error Vector Magnitude
Fast Recovery Mode
Full Sleep Mode
Frequency, Phase-to-DAC Output
5 MHz Channel Spacing
Adjacent Channel Leakage Ratio (ACLR)
OUT
OUT
OUT
OUT
= 25 MHz
= 50 MHz
= 100 MHz
= 20.1 MHz
= 98.6 MHz
= 201.1 MHz
= 397.8 MHz
3
Test Conditions/Comments
I/Q rate = 62.5 MSPS; 16× interpolation
2.5 Msymbols/s, QPSK, 4× oversampled
270.8333 ksymbols/s, GMSK, 32×
oversampled
2.5 Msymbols/s, 256-QAM, 4×
oversampled
High
High
IF = 143.88 MHz
Low
Rev. B | Page 6 of 64
Min
4
4
5
0
1
1.75
0
1.75
0
1.75
0
0.35
Typ
−167
−162
−157
−151
−82
−78
−73
0.53
0.77
−78
−78
70
2
250
1
8
5
79
Max
11
150
Unit
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBc
dBc
dBc
%
%
%
dBc
dBc
Mbps
ns
ns
ns
ns
ns
ns
SYNC_CLK
cycle
ns
ns
MHz
ns
ns
ns
ns
SYSCLK cycles
μs
SYSCLK cycles
SYSCLK cycles
4
4
4