STA310 STMicroelectronics, STA310 Datasheet - Page 27

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

5.4.1 Output precision and format selection
Output precision is selectable from 16 bits/word to 24 bits/word by setting the output precision select, in the PC-
MCONF (16-, 18-, 20- and 24-bit mode) register.
In 16-bit mode, data may be output either with the most significant bit first or least significant bit first. This is
configured by the contents of the field ORD in the PCMCONF register.
When PCMCONF.PREC is more than 16 bits, 32 bits are output for each channel. In this configuration, the field
FOR of register PCMCONF is used to select Sony or I²S- compatible format. The field DIF of PCMCONF is used
to position the 18, 20 or 24 bits either at the beginning or at the end of each 32-bit frame.
Figure 15. Output formats
M CONF.PEC
0:16-bit mode
0:16-bit mode
1:18-bit mode
1:18-bit mode
1:18-bit mode
1:18-bit mode
2:20-bit mode
2:20-bit mode
2:20-bit mode
2:20-bit mode
3:24-bit mode
3:24-bit mode
3:24-bit mode
3:24-bit mode
LRCLK
PCM_OUT[2:0]
PCM_OUT[2:0]
LRCLK
PCM_OUT[2:0]
PCM_OUT[2:0]
PCM_OUT[2:0]
PCM_OUT[2:0]
M
M
S
S
S
0
L
1
0
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CONF.ORD
16 SCLK cycles
M
S
PCM
18, 20 or 24 bits
MSB
0
18, 20 or 24 bits
32 SCLK cycles
M
M
S
S
NA
NA
0
0
1
1
0
0
1
1
0
0
1
1
S
M
L
S
CONF.FOR
18, 20 or 24 bits
18, 20 or 24 bits
M
S
S
L
PCM
16 SCLK cycles
L
S
S
L
0
NA
NA
0
1
0
1
0
1
0
1
0
1
0
1
0
CONF.DIF
PCM
M
S
L
S
S
L
S
L
M
S
0
PCMCONF.ORD = 1, PCMCONF.PREC is 16 bits mode
PCMCONF.ORD = 0, PCMCONF.PREC is 16 bits mode
M
S
18, 20 or 24 bits
MSB
0
18, 20 or 24 bits
{d23-d8}-{8*0}
{d23-d8}-{8*0}
{d23-d6}-{6*0}
{d23-d6}-{6*0}
{d23-d6}-{6*0}
{d23-d6}-{6*0}
{d23-d4}-{4*0}
{d23-d4}-{4*0}
{d23-d4}-{4*0}
{d23-d4}-{4*0}
{d23-d0}
{d23-d0}
{d23-d0}
{d23-d0}
DATA IN SAMPLE
MEMORY DATA
32 SCLK cycles
M
M
S
S
[23:0]
18, 20 or 24 bits
18, 20 or 24 bits
S
L
S
L
0
0
{d8-d23}: 16 bits
{d23-d8}: 16 bits
{13*0}{0}{d23-d6}: 32 bits
{0}{d23-d6}{13*0}: 32 bits
{14*d23}{d26*d6}: 32 bits
{d23-d6}{14*0}: 32 bits
{11*0}{0}{d23-d4}: 32 bits
{0}{d23-d4}{11*0}: 32 bits
{12*d23}{d23-d4}: 32 bits
{d23-d4}{12*0}: 32 bits
{6*0}{0}{d23-d0}: 32 bits
{0}{d23-d0}{7*0}: 32 bits
{8*d23}{d23-d0}: 32 bits
{d23-d0}{8*0}: 32 bits
PCM SERIAL OUTPUT
S
S
L
L
DATA SENT ON THE
(LEFT BIT FIRST)
PCMCONF.FOR = 1
PCMCONF.DIF = 1
PCMCONF.FOR = 0
PCMCONF.DIF = 0
PCMCONF.FOR = 0
PCMCONF.DIF = 1
PCMCONF.FOR = 1
PCMCONF.DIF = 0
STA310
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