STA310 STMicroelectronics, STA310 Datasheet - Page 42

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

STA310
PLLData
Address: 0x11
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
Data that must be written (has been read) at (from)
the address specified by PLL_ADD.
PLL_CMD
PLL Command
Address: 0x1D
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
PLL_ADD
42/90
RWCTL [1:0]
SYSPLLCTL
AUPLLCTL
7
7
Bitfield
6
6
5
4
Configure PCMCLK source and
direction.
00: No action is performed on the
configuration registers of the level 1
01: Read action of the configuration
registers. During this phase, the
content of a selectable (by PLL_ADD)
register of the level 1 is copied into the
PLL_DATA register.
10: Write action of the configuration
registers. During .this phase, the
content of a selectable (by PLL_ADD)
register of the level 1 is copied into the
PLL_DATA register.
11: Forbidden
System PLL coefficients transfert
0: No Transfer
1: Transfer the data between the level 1
and the level 2 for the system PLL
Audio PLL coefficient transfert
0: No Transfer
1: Transfer the data between the level 1
and the level 2 for the audio PLL
5
AUPLLCTL
4
3
Description
3
SYSPLLCTL RWCTL[1:0]
2
2
1
1
0
0
PLL Address
Address: 0x12
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
ENA_AU_FRACPLL
Audio PLL Enable
Address: 0xB5
Type: R/W
Software Reset: 1
Hardware Reset: 0
Description:
This register is used to enable the audio PLL of the
STA310. This register must be always set to “1” after
either a soft or hardware reset.
AU_PLL_FRACL_192
Frac Low Coefficient
Address: 0xB6
Address
Value
7
7
7
6
6
6
2: Disable System PLL
3: System PLL frac Low
4: System PLL frac High
6: System PLL N divider
7: System PLL X divider
8: System PLL M divider
9: System PLL update
10: Disable Audio PLL
11: Audio PLL Frac Low
12: Audio PLL Frac High
14: Audio PLL N divider
15: Audio PLL X divider
16: Audio PLL M divider
17: udio PLL update
Address of PLLs configuration registers
5
5
5
4
ADDRESS
4
4
FRACL
3
3
3
2
2
2
1
1
1
ENA_PLL
0
0
0