STA310 STMicroelectronics, STA310 Datasheet - Page 83

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

PCMV_STATUS2
Address : 0x78
Type: RW
Reset Value: UND
Description:
This register sets the dynamic range compression
from the first access unit. For the hexadecimal value
0x80, dynamic range control is not set. For all other
values, the dynamic range control is
(24.082 - 6.0206 * X - 0.2007 * Y)dB, where
X = dynamic_range_control[7..5] and
Y = dynamic_range_control[4..0].
LPCMV_CH_ASSIGN
Channel assignment
Address: 0xA8
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
PCMV_MULTI_CHS
Multi channels
Address: 0xA9
Type: R/W
Software Reset: NC
Hardware Reset: UND
Value
(decimal)
Value
7
7
7
Reserved
6
6
6
This register configures the audio channels:
See "DVD Specifications for Read-Only
Disc", Part 4 AUDIO SPECIFICATIONS,
Version 1.0, March 1999, Table C.1-2.
5
5
5
Dyn_Range_Control
Reserved
4
4
4
Description
3
3
3
2
Value
2
2
1
1
1
Value
0
0
0
Description:
9.24 MLP registers
MLP_CRC
CRC check
Address: 0x6C
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
This register controls the four different CRCs in MLP.
If the check is false, an error is returned (error num-
bers 80-83 in register and the outputs of all 6 chan-
nels are muted
MLP_DOWNMIX
Downmix
Address: 0x6F
Type: R/W
Software Reset: NC
Hardware Reset: UND
RH_C
MS_C
MA_C
SU_P
Bitfield
Value (decimal)
7
7
reserved
Value
6
6
1: Check of ’Restart_Header_CRC’ enable
1: Check of ’Major_Sync_CRC’ enable
1: Check of ’Max_Shift’ enable
1: Check of ’Substream_Parity’ enable
5
5
4
DWNMIX[7:0]
This register configures the multi
channel structure for the output
channels:
0: Stereo
1: Multi channels
SU_P MA_S MS_C
4
3
Description
3
Description
2
2
1
1
STA310
RH_C
0
83/90
0