STA310 STMicroelectronics, STA310 Datasheet - Page 55

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

Description:
This register indicates the status of the audio parser
for synchronization. It is used in conjunction with
PACKET_LOCK and SYNCK_LOCK registers. On
read the synchronization status interrupt bit is
cleared (INT.SYN is cleared).
ANCCOUNT
Ancillary data
Address : 0x41
Type: RO
Software Reset: UND
Hardware Reset: UND
Description:
This value gives the number of ancillary data in the
stream. The ancillary data interrupt bit ANC of the
register is cleared by a read.
HEAD4
HEADER 4 register
AC_3
Bitfield
FRA
PAC
7
0
7
6
0
Frame Status
0 0: Research audio synchronization
0 1: Wait for confirmation - a synchro word has
been detected but the parser has not yet
detected SYNC-LOCK+1
1 0: Synchronized - SYNC_LOCK + 1 synchro
words have been detected
1 1: Not used
Packet Status
0 0: Research packet synchronization word
0 1: Wait for confirmation - - a synchro word
has been detected but the parser has not yet
detected
1 0: Synchronized - PACKET_LOCK + 1
synchro words have been detected
1 1: Not used
6
PACKET_LOCK+1 synchro words.
5
0
5
4
0
4
Description
3
0
3
2
2
synchro words.
BSMOD
1
1
0
0
MPEG_2
OTHER
Address: 0x42
Type: RO
Software Reset: UND
Hardware Reset: UND
Description:
This register contains header data HEAD[31:24]. The
contents
frame.HEAD4[7:3] = 00000, in all cases.
When the host reads this register, the corresponding
interrupt bit (HDR) is cleared.
Dolby Digital
MPEG-2
OTHER
In all other types of frame HEAD4[2:0] = “000”
HEAD3
HEADER 3 register
Address: 0x43
Type: RO
Software Reset: UND
Hardware Reset: UND
Description:
HEAD4[2:0]
0
HEAD4[2]
HEAD4[1]
HEAD4[0]
0
7
0
Bitfield
Bitfield
0
0
6
0
depend
0
0
BSMOD if an Dolby Digital frame
0
DR=1 Dynamic range exists
K=0 in normal mode, K=1 in Karaoke
mode.
5
0
0
0
on
4
0
Description
Description
0
the
3
DTYPE
0
2
0
type
DR
1
0
STA310
of
55/90
K
0
0
the