STA310 STMicroelectronics, STA310 Datasheet - Page 47

• Manufacturer Part Number: STA310
• Description: IC AUDIO DECODER 6+2CH 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA310

• Applications: HDTV, Players, Receivers, Set-Top Boxes
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 3
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 32bit
• Sampling Rate: 192kHz
• Interface Type: I2C, Serial, Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8856; STA310

RVDLY
Right VCR channel delay
Address: 0xB0
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
Delay on right VCR channel, expressed in number of
group of 16 samples. RSDLY = delay (ms) * Fs (kHz)
/ 16.
When only one VCR channel is used, this register
must be reset at initialization.
UPDATE
PCM delay update
Address: 0x5D
Type: R/W
Address: 0x5E
Type: R/W
Software Reset: NC
Hardware Reset: UND
SPDIF_CAT
SPDIF_MODE[1:0]
AUX = ’0’
SPDIF_MODE[1:0]
AUX = ’1’
7
7
AUX
7
7
Bitfield
6
6
5
5
6
6
00: OFF, the IEC60958 is not working and the output line is idle,
01: MUTE, the outputs are PCM null data,
10: PCM, the outputs are PCM data and only the Left/Right channels are transmitted,
11: EMC, in this "encoded" mode the compressed bitstream is transmitted in IEC61937
standard.
10: PCM, the outputs are PCM data and only the "VCR" channels are transmitted.
All other values are reserved.
4
4
5
3
3
5
2
2
reserved
4
TM
1
1
DLY
4
0
0
3
CATCODE
Software Reset: 0
Hardware Reset 0
Description:
9.8 SPDIF output set-up
SPDIF_CMD
SPDIF control
This register controls the SPDIF mode:
Description:
Category code
DLY
TM
Bitfield
Description
2
3
This bit must be set to 1 to force the DSP to
update its delays values (read from the audio
delay registers).
0: Delay values held in the audio delay
registers are NOT updated in the DSP
(i.e. the DSP will keep the delay values set
previously)
1: The delay values held in the audio delay
registers are updated in the DSP (i.e. the
DSP will use the new values). This bit is
automatically reset to zero after it the update
has been carried out.
Set to “0”
2
1
SPDIF_MODE[1:0]
Description
1
0
STA310
0
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