CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 10

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

3.3
When multiple NSEs are cascaded to create large databases, the data being searched is presented to all NSEs simultaneously
in the cascaded system. If multiple matches occur, arbitration logic on the NSEs will enable the winning device (the one with
a matching entry closest to address 0 of the cascaded database) to drive the SRAM bus.
3.4
Pipeline latency is added to give enough time to a cascaded system’s arbitration logic to determine the device that will drive the
index of the matching entry on the SRAM bus. Pipeline logic adds latency to both the SRAM access cycles and the search
successful flag (SSF) and search successful flag valid (SSV) signals to align them to the host ASIC receiving the associated data.
3.5
Bit[0] in each of the 72-bit entries has a special purpose for the Learn command (0 = empty, 1 = full). When all the data entries
have bit[0] set to 1, the database asserts the FULL flag, indicating that all the NSEs in the depth-cascaded array are full.
4.0
Table 4-1 lists and describes all CYNSE70256 signals.
Table 4-1. CYNSE70256 Signal Description
Document #: 38-02035 Rev. *E
Clocks and Reset
Command and DQ Bus
CLK2X/CLK1X
CLK_MODE
CMD[10:0]
Pin Name
Arbitration Logic
Pipeline and SRAM Control
Full Logic
Signal Descriptions
PHS_L
CFG_L
RST_L
CMDV
Type
Pin
I
I
I
I
I
I
I
[1]
Clock Mode
CLK_MODE pin is LOW, CLK2X must be supplied on that pin. PHS_L must also be
supplied. If the CLK_MODE pin is HIGH, CLK1X must be supplied on the CLK2X/CLK1X
pin, and the PHS_L signal is not required. When the CLK_mode is HIGH, PHS_L is
unused and should be externally grounded.
Master Clock
be supplied. CYNSE70256 samples control and data signals on both edges of CLK1X (if
CLK1X is supplied). CYNSE70256 samples all data and control pins on the positive edge
of CLK2X (if the CLK2X and PHS_L signals are supplied). All signals are driven out of
the device on the rising edge of CLK1X (if CLK1X is supplied), and are driven on the rising
edge of CLK2X when PHS_L is LOW (if CLK2X is supplied).
Phase
from CLK2X. See Section 5.0, “Clocks,” on page 12.
Reset
Configuration
mode with CYNSE70032 and CYNSE70064. When CFG_L is LOW, the CMD[10:9]
should be externally grounded. With CFG_L LOW, the device will behave identically with
CYNSE70032 and CYNSE70064, and the new feature added to CYNSE70256 will be
disabled. When CFG_L is HIGH, the additional CMD[10:9] can be used and the following
additional features will be supported: 1. sixteen pairs of global masks are supported
instead of eight; 2. parallel Write to the data and mask arrays is supported (see
Subsection 10.5, “Parallel Write,” on page 24); and 3. configuring tables of up to three
different widths does not require table identification bits in the data array, thus saving two
bits from each 72-bit entry.
Command Bus
The descriptions of individual CMDs explains the details of the parameters. The encoding
of CMDs based on the [1:0] field are:
00: PIO Read
01: PIO Write
10: Search
11: Learn.
Command Valid
0: No command
1: Command.
. Driving RST_L LOW initializes the device to a known state.
. This signal runs at half the frequency of CLK2X and generates an internal CLK
. This signal allows the selection of clock input to the CLK1X/CLK2X pin. If the
. Depending on the CLK_MODE pin, either the CLK2X or the CLK1X must
. When CFG_L is LOW, CYNSE70256 will operate in backward compatibility
. [1:0] specifies the command; [10:2] contains the command parameters.
. This signal qualifies the command bus:
Pin Description
CYNSE70256
Page 10 of 109