CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 42

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

cycles A and B of the command) is also stored in both even and odd comparand register pairs, in each of the banks of all fifteen
devices, and selected by the comparand register index in command cycle B. In the ×72 configuration, the even comparand register
can be subsequently used by the Learn command only in the first non-full device. The word K (presented on the DQ bus in both
cycles A and B of the command) is compared with each entry in the table, starting at location 0. The first matching entry’s location
address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see “SRAM Addressing”
on page 86). The global winning device will drive the bus in a specific cycle. On global miss cycles, the device with LRAM = 1
and LDEV = 1 will be the default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 72-bit
searches in ×72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command
cycle (two CLK2X cycles) is shown in Table 10-14.
Table 10-14. Search Latency from Instruction to SRAM Access Cycle
For up to fifteen devices in the table (with TLSZ = 10), the latency of the Search from command to SRAM access cycle is 6. In
addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-15.
Table 10-15. Shift of SSF and SSV from SADR
10.6.3
The hardware diagram of the Search subsystem of four devices is shown in Figure 10-24. The following are parameters that are
programmed into the four devices.
Document #: 38-02035 Rev. *E
• First three devices (devices 0–2, banks 0 and 1): CFG = 0101010101010101, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0.
• First three devices (devices 3, Bank 0): CFG = 0101010101010101, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0.
• Fourth device (device 3, Bank 1): CFG = 0101010101010101, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1.
Number of Devices
1–15 (TLSZ = 10)
1–4 (TLSZ = 01)
144-bit Search on Tables Configured as ×144 using up to Four CYNSE70256 Devices
Will be same in each of the banks of each of the
HLAT
000
001
010
100
101
011
110
111
Must be same in each of the banks
of each of the fifteen devices
Comparand Register (odd)
Comparand Register (even)
fifteen devices
71
K
K
Figure 10-23. ×72 Table with Fifteen Devices
1920 K × 72 bits
Max Table Size
512K × 72 bits
0
1966079
Location
address
L
0
1
2
3
CFG = 0000000000000000
71
71
(72-bit configuration)
Number of CLK Cycles
GMR
K
0
1
2
3
4
5
6
7
Latency in CLK Cycles
0
0
(First matching entry)
5
6
CYNSE70256
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