CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 22

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-5. Read Address Format for Internal Registers
The Read operation lasts 4 + 2n CLK cycles (where n is the number of accesses in the burst specified by the BLEN field of the
RBURREG) in the sequence shown below. This operation assumes that the host ASIC has programmed the RBURREG of the
approprritae bank of the device with the starting ADR and the BLEN before initiating the burst Read command for the appropriate
bank in the appropriate device.
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the BLEN field of RBURREG are complete.
On the last transfer, the CYNSE70256 device drives the EOT signal HIGH.
At the termination of cycle (4 + 2n), the selected device floats the ACK line to a three-state condition. The burst Read instruction
is complete, and a new operation can begin. Table 10-6 describes the Read address format for data and mask arrays for burst
Read operations.
Table 10-6. Read Address Format for Data and Mask Arrays
10.4
The Write command can be a single Write of a data array, mask array, register, or external SRAM location (CMD[2] = 0). It can
be a burst Write (CMD[2] = 1) using an internal auto-incrementing address registers (WBURADR) of the data or mask array
Document #: 38-02035 Rev. *E
DQ[71:26] DQ[25:22]
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the address supplied
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[71:0] bus and drives ACK and EOT from Z to LOW.
• Cycle 5: The selected device drives the Read data from the address location on the DQ[71:0] bus and drives the ACK signal
• Cycle (4 + 2n): The selected device drives the DQ[71:0] to a three-state condition, and drives the ACK and EOT signals LOW.
Reserved
Reserved
on the DQ bus as shown in Table 10-6. The host ASIC selects the bank 0 or 1 (Based on Bank Bit) of the CYNSE70256 device
where ID[4:1] matches the DQ[25:22] lines. DQ[21] specfies the bank of the device that is written. If DQ[25:21] = 11111 the
host ASIC selects the bank of the CYNSE70256 device with the LDEV bit set.
HIGH.
DQ[71:26]
Reserved
Write Command
ID
ID
CMD[10:2]
CMD[1:0]
CMDV
CLK2X
PHS_L
Bank 0 or 1 00: Data Array Reserved
Bank 0 or 1 01: Mask Array Reserved
DQ[25:22]
ACK
EOT
DQ[21]
DQ
Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
ID
Address
cycle
Read
A B
DQ[20:19]
1
Bank 0 or 1
DQ[21]
cycle
2
cycle
3
cycle
DQ[18:16]
FF
4
cycle
Data0
11: Register
5
DQ[20:19]
cycle
6
FF
Do not care
which increments for each access.
Do not care
which increments for each access.
cycle
Data1
7
cycle
8
FF
. These seventeen bits come from the RBURADR,
. These seventeen bits come from the RBURADR,
cycle
Data2
9
Reserved
DQ[18:7]
cycle
10
FF
cycle
11
Data3
DQ[15:0]
cycle
12
Register Address
CYNSE70256
DQ[6:0]
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