CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 13

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 7-1. Register Overview (Bank0 and Bank1)
6.0
When the device first powers up, it takes 0.5 ms to lock the internal PLL. During this PLL, the RST_L must be held LOW for proper
initialization of the device. It also takes 32 extra CLK1X cycles in CLK1X mode and 64 extra cycles in CLK2X mode. Setup and
hold requirements will change in CLK1X mode if the duty cycle of the CLK1X is varied. All signals to the device in CLK1X mode
are sampled by a clock that is generated by multiplying CLK1X by two. Since the PLL has a locking range, the device will only
work between the range of frequencies specified in the timing specification section of this datasheet.
7.0
All registers in the CYNSE70256 device are 72 bits wide. The CYNSE70256 contains two banks of sixteen pairs of comparand
storage registers, sixteen pairs of GMRs, eight search successful index registers, and one each of command, information, burst
Read, burst Write, and next-free address registers. Table 7-1 provides an overview of all the CYNSE70256 registers. The
registers are in ascending address order; each register group is described in the following subsections.
7.1
The device contains two banks of 32 72-bit comparand registers (sixteen pairs) dynamically selected in every Search operation
to store the comparand presented on the DQ bus. The Learn command will later use these registers when it is executed. The
CYNSE70256 device stores the Search command’s cycle A comparand in the even-numbered register and the cycle B
comparand in the odd-numbered register, as shown in Figure 7-1 for each of the two banks of registers.
Document #: 38-02035 Rev. *E
Address
96–111
32–47
48–55
61–63
0–31
56
57
58
59
60
Comparand Registers
Phase-Lock Loop Usage
Registers
Use for CLK2X mode
Use for CLK1X mode
Abbreviation
COMMAND
COMP0–31
WBURREG
RBURREG
SSR0–7
MASKS
INFO
CLK2X
PHS_L
NFA
CLK1X
–
Figure 5-3. CYNSE70256 Clocks for All Timing Diagrams
Type
RW
RW
RW
RW
R
R
R
R
–
Sixteen pairs of comparand registers that store comparands from the
DQ bus for learning later.
Sixteen GMR pairs.
Eight search successful index registers.
Command register.
Information register.
Burst Read register.
Burst Write register.
Next-free address register.
Reserved.
Name
CYNSE70256
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