CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 7

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

CYNSE70256
LIST OF TABLES
Table 4-1. CYNSE70256 Signal Description ........................................................................................ 10
Table 7-1. Register Overview (Bank0 and Bank1) ............................................................................... 13
Table 7-2. Search Successful Register Description .............................................................................15
Table 7-3. Command Register Description ........................................................................................... 15
Table 7-4. Information Register Description ......................................................................................... 16
Table 7-5. Read Burst Register Description ......................................................................................... 16
Table 7-6. Write Burst Register Description ......................................................................................... 17
Table 7-7. NFA Register ....................................................................................................................... 17
Table 8-1. Bit Position Match ................................................................................................................ 18
Table 10-1. Command Codes ............................................................................................................... 19
Table 10-2. Command Parameters ...................................................................................................... 20
Table 10-3. Read Command Parameters ............................................................................................. 20
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM ........................................... 21
Table 10-5. Read Address Format for Internal Registers ..................................................................... 22
Table 10-6. Read Address Format for Data and Mask Arrays .............................................................. 22
Table 10-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write) ..................... 23
Table 10-8. Write Address Format for Internal Registers ..................................................................... 23
Table 10-9. Write Address Format for Data and Mask Array (Burst Write) .......................................... 24
Table 10-10. Hit/Miss Assumptions ...................................................................................................... 25
Table 10-11. Search Latency from Instruction to SRAM Access Cycle ................................................ 29
Table 10-12. Shift of SSF and SSV from SADR ................................................................................... 29
Table 10-13. Hit/Miss Assumptions ...................................................................................................... 30
Table 10-14. Search Latency from Instruction to SRAM Access Cycle ................................................ 42
Table 10-15. Shift of SSF and SSV from SADR ................................................................................... 42
Table 10-16. Hit/Miss Assumptions ...................................................................................................... 43
Table 10-17. Search Latency from Instruction to SRAM Access Cycle ................................................ 47
Table 10-18. Shift of SSF and SSV from SADR ................................................................................... 47
Table 10-19. Hit/Miss Assumptions ...................................................................................................... 48
Table 10-20. Search Latency from Instruction to SRAM Access Cycle ................................................ 61
Table 10-21. Shift of SSF and SSV from SADR ................................................................................... 61
Table 10-22. Hit/Miss Assumptions ...................................................................................................... 62
Table 10-23. Search Latency from Instruction to SRAM Access Cycle ................................................ 66
Table 10-24. Shift of SSF and SSV from SADR ................................................................................... 66
Table 10-25. Hit/Miss Assumptions ...................................................................................................... 67
Table 10-26. Search Latency from Instruction to SRAM Access Cycle ................................................ 80
Table 10-27. Shift of SSF and SSV from SADR ................................................................................... 80
Table 10-28. Searches with CFG_L Set HIGH .....................................................................................82
Table 10-29. SRAM Write Cycle Latency from Second Cycle of Learn Instruction .............................. 83
Table 12-1. SRAM Bus Address ........................................................................................................... 86
Table 15-1. Supported Operations ....................................................................................................... 96
Table 15-2. TAP Device ID Register ..................................................................................................... 96
Table 16-1. DC Electrical Characteristics for CYNSE70256 ................................................................ 97
Table 16-2. Operating Conditions for CYNSE70256 ............................................................................ 97
Table 17-1. AC Timing Parameters with CLK2X .................................................................................. 98
Table 17-2. AC Timing Parameters with CLK1X .................................................................................. 98
Table 17-3. AC Table for Test Condition of CYNSE70256 ................................................................... 99
Table 18-1. Pinout Descriptions for Pinout Diagram ........................................................................... 102
Table 19-1. Ordering Information ........................................................................................................ 107
Document #: 38-02035 Rev. *E
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