CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 20

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-2. Command Parameters
10.3
The Read can be a single Read of a data array, a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst
Read of the data (CMD[2] = 1) or mask array locations using an internal auto-incrementing address register (RBURADR).
A description of each type is provided in Table 10-3. A single-location Read operation lasts six cycles, as shown in Figure 10-1.
The burst Read adds two cycles for each successive Read. The SADR[23:21] bits supplied in Read instruction cycle A drives
SADR[23:21] signals during a Read of an SRAM location.
Table 10-3. Read Command Parameters
Notes:
Document #: 38-02035 Rev. *E
10. The device registers and external SRAM can only be read in single-Read mode.
7.
8.
9.
CMD Parameter
CMD
Learn
Search
Read
Write
Use CMD[8:0] only and connect CMD[10:9] to ground with CFG_L LOW.
For a description of CMD[9] and CMD[2], see Search 288-bit-configured tables and mixed-size searches with CFG_L HIGH.
The 288-bit-configured devices or 288-bit-configured quadrants within devices do not support the Learn instruction.
CMD[2]
[7,8]
[9]
0
1
Read Command
CYC
A
B
A
B
A
B
A
B
Index
Index
Index
Read Command
GMR
GMR
GMR
10
Single Read
X
X
X
X
X
Burst Read
[9]
[9]
[9]
288 bits: X
144 bits: 1
1: Parallel
1: Parallel
0: Normal
0: Normal
72 bits: 0
Write
Write
Write
Write
X
X
X
X
9
Reads a single location of the data array, mask array, external SRAM, or device registers.
All access information is applied on the DQ bus.
Reads a block of locations from the data or mask array as a burst. RBURADR specifies
the starting address and the length of the data transfer from the data or mask array; it also
auto-increments the address for each access. All other access information is applied on
the DQ bus.
SADR[23] SADR[22] SADR[21]
SADR[23] SADR[22] SADR[21]
SADR[23] SADR[22] SADR[21]
SADR[23] SADR[22] SADR[21]
8
0
0
0
[10]
SSR Index[2:0]
7
0
0
0
1: 144 bits
0: 72 bits
Mode
6
0
0
Description
5
0
0
GMR Index
GMR Index
GMR Index
[2:0]
[2:0]
[2:0]
Comparand Register Index
Comparand Register Index
Comparand Register Index
4
0
0
3
0
0
72 bits or 144 bits: 0
0 in second cycle
1 in first cycle
0 = Single
0 = Single
0 = Single
0 = Single
1 = Burst
1 = Burst
1 = Burst
1 = Burst
288 bits:
2
CYNSE70256
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1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1